公开(公告)号：US20220199047A1

公开(公告)日：2022-06-23

申请号：US17131209

申请日：2020-12-22

Applicant: ATI Technologies ULC

Inventor： Arshad Rahman ,  Rajeevan Panchacharamoorthy ,  Boris Ivanovic

IPC: G09G3/36 ,  G09G5/00 ,  G11C7/10 ,  G11C7/22

Abstract: Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.

公开(公告)号：US11699408B2

公开(公告)日：2023-07-11

申请号：US17131209

申请日：2020-12-22

Applicant: ATI Technologies ULC

Inventor： Arshad Rahman ,  Rajeevan Panchacharamoorthy ,  Boris Ivanovic

IPC: G09G3/36 ,  G09G5/00 ,  G11C7/22 ,  G11C7/10

CPC classification number: G09G3/3618 ,  G09G5/001 ,  G09G5/006 ,  G11C7/1072 ,  G11C7/222

Abstract: Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.

公开(公告)号：US11430410B2

公开(公告)日：2022-08-30

申请号：US16889318

申请日：2020-06-01

Applicant: ATI TECHNOLOGIES ULC

Inventor： Jun Lei ,  Syed Athar Hussain ,  David I. J. Glen ,  Rajeevan Panchacharamoorthy ,  Fatemeh Amirnavaei ,  David Galiffi ,  Arshad Rahman ,  Boris Ivanovic

IPC: G09G5/12 ,  G06F3/14

Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.

公开(公告)号：US11948534B2

公开(公告)日：2024-04-02

申请号：US17877540

申请日：2022-07-29

Applicant: ATI TECHNOLOGIES ULC

Inventor： Jun Lei ,  Syed Athar Hussain ,  David I. J. Glen ,  Rajeevan Panchacharamoorthy ,  Fatemeh Amirnavaei ,  David Galiffi ,  Arshad Rahman ,  Boris Ivanovic

IPC: G09G5/12 ,  G06F3/14

CPC classification number: G09G5/12 ,  G06F3/1431 ,  G06F3/1446 ,  G09G2360/04

Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.