公开(公告)号：US20210026797A1

公开(公告)日：2021-01-28

申请号：US16521562

申请日：2019-07-24

Applicant: ATI Technologies ULC

Inventor： Natale Barbiero ,  Gordon Caruk

IPC: G06F13/42 ,  G06F13/20

Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.

公开(公告)号：US20190012760A1

公开(公告)日：2019-01-10

申请号：US15864234

申请日：2018-01-08

Applicant: ATI Technologies ULC

Inventor： Grigori Temkine ,  Gordon Caruk ,  Oleg Drapkin

IPC: G06T1/20 ,  G09G5/36

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

公开(公告)号：US20160364834A1

公开(公告)日：2016-12-15

申请号：US15229679

申请日：2016-08-05

Applicant: ATI Technologies ULC

Inventor： Grigori Temkine ,  Gordon Caruk ,  Oleg Drapkin

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T2200/28 ,  G06T2210/52 ,  G09G5/363

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract translation: 公开了一种用于提供多种图形处理能力的方法和装置，同时利用桥接电路上的未使用的集成图形处理电路以及外部或分立的图形处理单元。 特别地，桥接电路包括被配置为处理图形作业的集成图形处理电路。 桥接电路还包括根据与分立图形处理电路的接口可操作的接口。 控制器包括在桥接电路中，并且每当离散图形处理电路耦合到接口时响应，使得集成图形处理电路结合图形处理电路的任务结合可分离的图形处理电路 处理图形作业的另一个任务。 还公开了相应的方法。

公开(公告)号：US09865030B2

公开(公告)日：2018-01-09

申请号：US15229679

申请日：2016-08-05

Applicant: ATI Technologies ULC

Inventor： Grigori Temkine ,  Gordon Caruk ,  Oleg Drapkin

IPC: G06T1/20 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06T2200/28 ,  G06T2210/52 ,  G09G5/363

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

公开(公告)号：US10936530B2

公开(公告)日：2021-03-02

申请号：US16521562

申请日：2019-07-24

Applicant: ATI Technologies ULC

Inventor： Natale Barbiero ,  Gordon Caruk

IPC: G06F13/42 ,  G06F13/20

Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.

公开(公告)号：US09424622B2

公开(公告)日：2016-08-23

申请号：US13924958

申请日：2013-06-24

Applicant: ATI TECHNOLOGIES, ULC

Inventor： Grigori Temkine ,  Gordon Caruk ,  Oleg Drapkin

IPC: G06F15/80 ,  G06F15/16 ,  G06T1/20 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06T2200/28 ,  G06T2210/52 ,  G09G5/363

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

公开(公告)号：US20140035936A1

公开(公告)日：2014-02-06

申请号：US13924958

申请日：2013-06-24

Applicant: ATI TECHNOLOGIES, ULC

Inventor： Grigori Temkine ,  Gordon Caruk

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T2200/28 ,  G06T2210/52 ,  G09G5/363

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract translation: 公开了一种用于提供多种图形处理能力的方法和装置，同时利用桥接电路上的未使用的集成图形处理电路以及外部或分立的图形处理单元。 特别地，桥接电路包括被配置为处理图形作业的集成图形处理电路。 桥接电路还包括根据与分立图形处理电路的接口可操作的接口。 控制器包括在桥接电路中，并且每当离散图形处理电路耦合到接口时响应，使得集成图形处理电路结合图形处理电路的任务结合可分离的图形处理电路 处理图形作业的另一个任务。 还公开了相应的方法。

公开(公告)号：US20230342325A1

公开(公告)日：2023-10-26

申请号：US18216908

申请日：2023-06-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F13/1689 ,  G06F2213/0026

Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

公开(公告)号：US11693813B2

公开(公告)日：2023-07-04

申请号：US16427020

申请日：2019-05-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F13/1689 ,  G06F2213/0026

Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

公开(公告)号：US20220035765A1

公开(公告)日：2022-02-03

申请号：US17503959

申请日：2021-10-18

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Gerald R. Talbot

IPC: G06F13/42 ,  G06F13/12 ,  G06F13/40

Abstract: An interconnect controller for a data processing platform includes a data link layer controller for selectively receiving data packets from and sending data packets to a higher protocol layer, and a physical layer controller coupled to the data link layer controller and adapted to be coupled to a communication link. The physical layer controller operates according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount. In response to performing a link initialization, the interconnect controller performs at least one setup operation to select a speed, and subsequently operates the communication link using a selected speed.