公开(公告)号：US20250141464A1

公开(公告)日：2025-05-01

申请号：US18497605

申请日：2023-10-30

Applicant: Avago Technologies International Sales Pte. Limited

Inventor： Chang Liu ,  Boyu Hu ,  Xiaoliang Li ,  Delong Cui ,  Jun Cao

IPC: H03M1/44

Abstract: A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.

公开(公告)号：US11916561B1

公开(公告)日：2024-02-27

申请号：US17582641

申请日：2022-01-24

Applicant: Avago Technologies International Sales Pte. Limited

Inventor： Boyu Hu ,  Chang Liu ,  Guansheng Li ,  Haitao Wang ,  Delong Cui ,  Jun Cao

IPC: H03M1/06 ,  G06F1/06 ,  H03K5/13 ,  H03L7/087 ,  H03K5/00

CPC classification number: H03M1/0607 ,  G06F1/06 ,  H03K5/13 ,  H03L7/087 ,  H03K2005/00052

Abstract: An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.

公开(公告)号：US10541679B1

公开(公告)日：2020-01-21

申请号：US16170068

申请日：2018-10-25

Applicant: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED

Inventor： Yong Liu ,  Chang Liu ,  Delong Cui ,  Jun Cao

IPC: H03K3/356 ,  H03K17/082

Abstract: Various aspects of amplifying amplitude of a pulse are disclosed herein. In sonic embodiments, a device includes driver circuitry that receives an input pulse swinging or transitioning between a first reference voltage and a second reference voltage higher than the first reference voltage, In some embodiments, the driver circuitry generates a driving pulse swinging between a third reference voltage and the second reference voltage according to the input pulse, where the third reference voltage is between the first reference voltage and the second reference voltage. In some embodiments, the device further includes a transistor coupled to the driver circuitry. In some embodiments, the transistor outputs an output pulse swinging between the first reference voltage and an output voltage according to the driving pulse from the driver circuitry, where the output voltage is higher than the second reference voltage.