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公开(公告)号：US20240364334A1
公开(公告)日：2024-10-31
申请号：US18141344
申请日：2023-04-28
发明人： Hyung-Joon Jeon , Jun Cao , Seong Ho Lee , Anand J. Vasani
IPC分类号： H03K17/693
CPC分类号： H03K17/693
摘要： In some implementations, the device may include a first circuit receiving an input signal having a first frequency, the first circuit including a first node and a second node. The device may include a second circuit receiving an input signal having a second frequency different from the first frequency, the second circuit including a first node and a second node, a first inductor coupled between the first node of the first circuit and the first node of the second circuit. The device may include a second inductor coupled between the second node of the first circuit and the second node of the second circuit, a first switch coupled between the first node of the second circuit and the second node of the second circuit, at least one differential inductor formed of the first inductor and the second inductor in response to the first switch being in a closed state.
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公开(公告)号：US20240333300A1
公开(公告)日：2024-10-03
申请号：US18126924
申请日：2023-03-27
CPC分类号： H03M1/462 , H03M1/0607
摘要： An analog-to-digital converter (ADC) circuit includes a digital-to-analog converter (DAC) circuit, a comparator circuit, an encoder, and a compensation circuit. The DAC circuit receives a reference voltage and provides an output signal based on the reference voltage. The comparator circuit compares the output signal with an analog input signal and generates a comparison signal. A reset command is generated based on the output signal being greater than the analog input signal. The encoder splits a ripple associated with the reference voltage into multiple pulses in response to a reset command. The compensation circuit generates, responsive to the reset command, compensation pulses to compensate the multiple pulses.
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3.发明公开公开(公告)号：US20240154591A1
公开(公告)日：2024-05-09
申请号：US18335217
申请日：2023-06-15
发明人： Jiawen Zhang , Delong Cui , Afshin Momtaz , Kun Chuai , Jun Cao
CPC分类号： H03F3/45475 , G01J1/44 , H03G3/30 , H03F2200/372 , H03G2201/103
摘要： An optical module includes an optical receiver with a complementary metal-oxide semiconductor (CMOS) transimpedance amplifier (TIA) and a digital signal processing (DSP) circuit. The DSP circuit is integrated with the CMOS TIA and facilitates adaptability of the CMOS TIA, and the CMOS TIA can adapt by using information provided by the DSP circuit.
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4.发明授权公开(公告)号：US11929756B2
公开(公告)日：2024-03-12
申请号：US17694225
申请日：2022-03-14
发明人： Yong Liu , Jun Cao , Delong Cui
CPC分类号： H03M1/1028 , H03M1/1009 , H03M1/1245 , H03M1/46
摘要： Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.
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公开(公告)号：US20240072770A1
公开(公告)日：2024-02-29
申请号：US17898175
申请日：2022-08-29
发明人： Lakshmi RAO , Siavash Fallahi , Tim Yee He , Ali Nazemi , Jun Cao
摘要： A device is provided that includes a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal; and a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.
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公开(公告)号：US20230327663A1
公开(公告)日：2023-10-12
申请号：US17718139
申请日：2022-04-11
发明人： Guansheng Li , Delong Cui , Jun Cao
IPC分类号： H03K17/60
CPC分类号： H03K17/602 , H04B10/40
摘要： A system including a source follower circuit is disclosed. The source follower circuit configured as a voltage buffer that includes a first common-drain transistor that passes an input signal at the gate to an output loading capacitor at the source, and a second common-drain transistor that is used as a bias current source. The source follower circuit includes a first resistor at the drain of the first transistor generating a first voltage that is fed back through a first path through the gate of the second transistor so as to produce additional current to help the output signal catch up with the input voltage. The source follower circuit further includes an inductive element and bias circuit, which along with the first resistor, increases bandwidth and reduced settling time.
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公开(公告)号：US20230327623A1
公开(公告)日：2023-10-12
申请号：US17716181
申请日：2022-04-08
发明人： Guansheng Li , Heng Zhang , Delong Cui , Jun Cao
CPC分类号： H03F3/607 , H03F3/211 , H03F2200/423 , H03F2200/294 , H03F1/18
摘要： Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.
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公开(公告)号：US10931288B2
公开(公告)日：2021-02-23
申请号：US16727601
申请日：2019-12-26
发明人： Zhiyu Ru , Tim Yee He , Siavash Fallahi , Ali Nazemi , Delong Cui , Jun Cao
摘要： Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.
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公开(公告)号：US12068748B2
公开(公告)日：2024-08-20
申请号：US17898175
申请日：2022-08-29
发明人： Lakshmi Rao , Siavash Fallahi , Tim Yee He , Ali Nazemi , Jun Cao
摘要： A device is provided that includes a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal; and a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.
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公开(公告)号：US20240257847A1
公开(公告)日：2024-08-01
申请号：US18103696
申请日：2023-01-31
发明人： Vadim Milirud , Guansheng Li , Seong-Ho Lee , Jun Cao , Yong Liu
CPC分类号： G11C7/16 , G11C7/1039 , G11C7/222
摘要： Described herein are systems and methods related to a device including an analog-to-digital converter (DAC) configured to convert a digital signal into an analog signal. The systems and methods can receive an analog signal at a first input, and provide the analog signal to a first output in response to a first clock signal. The first clock signal has a level at least partially dependent on the analog signal. The systems and methods can provide a path to a ground node for the first clock signal in response to a second clock signal. The second clock signal is independent of the analog signal.
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