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公开(公告)号：US20240413827A1
公开(公告)日：2024-12-12
申请号：US18330719
申请日：2023-06-07
Inventor： Yonghyun Shim , YU-Ming Ying , Guansheng Li , Delong Cui , Jun Cao
Abstract: A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.
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2.发明授权公开(公告)号：US11722109B1
公开(公告)日：2023-08-08
申请号：US17980478
申请日：2022-11-03
Inventor： Jiawen Zhang , Delong Cui , Afshin Momtaz , Kun Chuai , Jun Cao
CPC classification number: H03F3/45475 , G01J1/44 , H03G3/30 , H03F2200/372 , H03G2201/103
Abstract: An optical module includes an optical receiver with a complementary metal-oxide semiconductor (CMOS) transimpedance amplifier (TIA) and a digital signal processing (DSP) circuit. The DSP circuit is integrated with the CMOS TIA and facilitates adaptability of the CMOS TIA, and the CMOS TIA can adapt by using information provided by the DSP circuit.
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公开(公告)号：US20230353173A1
公开(公告)日：2023-11-02
申请号：US17733219
申请日：2022-04-29
Inventor： Xiaochen Yang , Hamid Hatamkhani , Guansheng Li , Yong Liu , Delong Cui , Jun Cao
CPC classification number: H04B1/04 , H04B1/0003 , H04B2001/0425 , H04B2001/0416
Abstract: Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.
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4.发明公开公开(公告)号：US20230299785A1
公开(公告)日：2023-09-21
申请号：US17700166
申请日：2022-03-21
Inventor： Ullas Singh , Namik Kocaman , Mohammadamin Torabi , Meisam Honarvar Nazari , Mehmet Batuhan Dayanik , Delong Cui , Jun Cao
CPC classification number: H03M1/462 , H03M1/0697 , H03M1/468
Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.
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公开(公告)号：US10903846B1
公开(公告)日：2021-01-26
申请号：US16867358
申请日：2020-05-05
Inventor： Yong Liu , Delong Cui , Jun Cao
Abstract: Disclosed herein are related to systems and methods for a power efficient successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a sample and digital to analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of storage circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of storage circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of multiple bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the multiple bits during a corresponding time period.
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Patent Agency Ranking
公开(公告)号：US10541679B1
公开(公告)日：2020-01-21
申请号：US16170068
申请日：2018-10-25
Inventor： Yong Liu , Chang Liu , Delong Cui , Jun Cao
IPC: H03K3/356 , H03K17/082
Abstract: Various aspects of amplifying amplitude of a pulse are disclosed herein. In sonic embodiments, a device includes driver circuitry that receives an input pulse swinging or transitioning between a first reference voltage and a second reference voltage higher than the first reference voltage, In some embodiments, the driver circuitry generates a driving pulse swinging between a third reference voltage and the second reference voltage according to the input pulse, where the third reference voltage is between the first reference voltage and the second reference voltage. In some embodiments, the device further includes a transistor coupled to the driver circuitry. In some embodiments, the transistor outputs an output pulse swinging between the first reference voltage and an output voltage according to the driving pulse from the driver circuitry, where the output voltage is higher than the second reference voltage.
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公开(公告)号：US11916561B1
公开(公告)日：2024-02-27
申请号：US17582641
申请日：2022-01-24
Inventor： Boyu Hu , Chang Liu , Guansheng Li , Haitao Wang , Delong Cui , Jun Cao
CPC classification number: H03M1/0607 , G06F1/06 , H03K5/13 , H03L7/087 , H03K2005/00052
Abstract: An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.
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公开(公告)号：US11658648B1
公开(公告)日：2023-05-23
申请号：US17589682
申请日：2022-01-31
Inventor： Hyung-Joon Jeon , Yonghyun Shim , Delong Cui , Jun Cao
CPC classification number: H03K5/135 , H03L7/085 , H03K2005/00052 , H03L7/0807
Abstract: A system includes a sampler, a receiver phase-locked loop circuit configured to provide one or more input clock signals, and a phase interpolation circuit coupled to the receiver phase-locked loop circuit and the sampler. The phase interpolation circuit further includes a first phase interpolator configured to generate a first recovered clock signal based on the one or more input clock signals and a first code, and a second phase interpolator configured to generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolation code offset from the first code, wherein the interpolation code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal, wherein the outputs of the first phase interpolator and second phase interpolator are configured to be merged.
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公开(公告)号：US10523220B1
公开(公告)日：2019-12-31
申请号：US16356747
申请日：2019-03-18
Inventor： Zhiyu Ru , Tim Yee He , Siavash Fallahi , Ali Nazemi , Delong Cui , Jun Cao
Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.
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公开(公告)号：US12212334B2
公开(公告)日：2025-01-28
申请号：US17700166
申请日：2022-03-21
Inventor： Ullas Singh , Namik Kocaman , Mohammadamin Torabi , Meisam Honarvar Nazari , Mehmet Batuhan Dayanik , Delong Cui , Jun Cao
Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.
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