公开(公告)号：US06509773B2

公开(公告)日：2003-01-21

申请号：US09844266

申请日：2001-04-30

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03H1116

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US07016449B2

公开(公告)日：2006-03-21

申请号：US09844432

申请日：2001-04-30

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03D3/24 ,  H04L7/00

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US06791388B2

公开(公告)日：2004-09-14

申请号：US10346210

申请日：2003-01-17

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03H1116

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US07058150B2

公开(公告)日：2006-06-06

申请号：US09844441

申请日：2001-04-30

申请人： Aaron W. Buchwald ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H04L7/00

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US07012983B2

公开(公告)日：2006-03-14

申请号：US09844296

申请日：2001-04-30

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03D3/34 ,  H04L7/00

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US06995594B2

公开(公告)日：2006-02-07

申请号：US10855392

申请日：2004-05-28

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03H11/16

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US08433020B2

公开(公告)日：2013-04-30

申请号：US11446144

申请日：2006-06-05

申请人： Aaron W. Buchwald ,  Michael Le ,  Josephus Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Michael Le ,  Josephus Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H04L7/00

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US08223828B2

公开(公告)日：2012-07-17

申请号：US11976185

申请日：2007-10-22

申请人： Aaron Buchwald ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron Buchwald ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discrete-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

摘要翻译： 用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。 在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。 自适应控制逻辑由模拟和/或数字组件实现。 在一个实施例中，本发明使模拟数据信号的离散时间模拟表示相等。 在一个实施例中，本发明数字地控制均衡参数。 在一个实施例中，所得到的均衡的模拟数据信号被数字化。 在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。 然后将均衡的样品数字化。 本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

公开(公告)号：US08472512B2

公开(公告)日：2013-06-25

申请号：US13467531

申请日：2012-05-09

申请人： Aaron Buchwald ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron Buchwald ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.

摘要翻译： 用于自适应地均衡用于信号路径的模拟信息信号的方法和系统，包括对模拟信息信号进行采样，从而产生模拟采样，并对模拟采样进行均衡处理，其中均衡包括处理平均过渡后样本幅度 以及模拟样本的稳态样本幅度的平均值，以产生均衡的模拟样本。

公开(公告)号：US20120243598A1

公开(公告)日：2012-09-27

申请号：US13467531

申请日：2012-05-09

申请人： Aaron Buchwald ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron Buchwald ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03H7/00

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.

摘要翻译： 用于自适应地均衡用于信号路径的模拟信息信号的方法和系统，包括对模拟信息信号进行采样，从而产生模拟采样，并对模拟采样进行均衡处理，其中均衡包括处理平均过渡后样本幅度 以及模拟样本的稳态样本幅度的平均值，以产生均衡的模拟样本。