公开(公告)号：US06509773B2

公开(公告)日：2003-01-21

申请号：US09844266

申请日：2001-04-30

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03H1116

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US07012983B2

公开(公告)日：2006-03-14

申请号：US09844296

申请日：2001-04-30

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03D3/34 ,  H04L7/00

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US07016449B2

公开(公告)日：2006-03-21

申请号：US09844432

申请日：2001-04-30

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03D3/24 ,  H04L7/00

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US06791388B2

公开(公告)日：2004-09-14

申请号：US10346210

申请日：2003-01-17

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03H1116

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US06995594B2

公开(公告)日：2006-02-07

申请号：US10855392

申请日：2004-05-28

申请人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H03H11/16

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US07058150B2

公开(公告)日：2006-06-06

申请号：US09844441

申请日：2001-04-30

申请人： Aaron W. Buchwald ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H04L7/00

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US08433020B2

公开(公告)日：2013-04-30

申请号：US11446144

申请日：2006-06-05

申请人： Aaron W. Buchwald ,  Michael Le ,  Josephus Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

发明人： Aaron W. Buchwald ,  Michael Le ,  Josephus Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC分类号： H04L7/00

CPC分类号： H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US08351560B2

公开(公告)日：2013-01-08

申请号：US13238314

申请日：2011-09-21

申请人： Aaron W. Buchwald ,  Michael Le ,  Hui Wang ,  Howard A. Baumer ,  Pieter Vorenkamp

发明人： Aaron W. Buchwald ,  Michael Le ,  Hui Wang ,  Howard A. Baumer ,  Pieter Vorenkamp

IPC分类号： H04L7/00

CPC分类号： H04L7/0091 ,  H04L7/0025 ,  H04L7/0029 ,  H04L25/20

摘要： A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

摘要翻译： 提供了一种用于基于相位插值器的传输时钟控制的系统和方法。 该系统包括具有耦合到主定时发生器和传输模块的相位插值器的发射机。 相位插值器还耦合到接收器插值器控制模块和/或外部插值器控制模块。 当系统以重复模式运行时，发射机相位插值器从接收器插值器控制模块接收控制信号。 发射机相位内插器使用信号将传输时钟同步到采样时钟。 当系统在测试模式下操作时，用户在外部插值器控制模块中定义传输数据简档。 外部内插器控制模块基于轮廓生成控制信号。 发射机相位内插器使用该信号来生成传输模块使用的传输时钟，以生成具有所需简档的数据流。

公开(公告)号：US20120008701A1

公开(公告)日：2012-01-12

申请号：US13238314

申请日：2011-09-21

申请人： Aaron W. Buchwald ,  Michael Le ,  Hui Wang ,  Howard A. Baumer ,  Pieter Vorenkamp

发明人： Aaron W. Buchwald ,  Michael Le ,  Hui Wang ,  Howard A. Baumer ,  Pieter Vorenkamp

IPC分类号： H04L7/00

CPC分类号： H04L7/0091 ,  H04L7/0025 ,  H04L7/0029 ,  H04L25/20

摘要： A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

摘要翻译： 提供了一种用于基于相位插值器的传输时钟控制的系统和方法。 该系统包括具有耦合到主定时发生器和传输模块的相位插值器的发射机。 相位插值器还耦合到接收器插值器控制模块和/或外部插值器控制模块。 当系统以重复模式运行时，发射机相位插值器从接收器插值器控制模块接收控制信号。 发射机相位内插器使用信号将传输时钟同步到采样时钟。 当系统在测试模式下操作时，用户在外部插值器控制模块中定义传输数据简档。 外部内插器控制模块基于轮廓生成控制信号。 发射机相位内插器使用该信号来生成传输模块使用的传输时钟，以生成具有所需简档的数据流。

公开(公告)号：US08050373B2

公开(公告)日：2011-11-01

申请号：US10876602

申请日：2004-06-28

申请人： Aaron W. Buchwald ,  Michael Le ,  Hui Wang ,  Howard A. Baumer ,  Pieter Vorenkamp

发明人： Aaron W. Buchwald ,  Michael Le ,  Hui Wang ,  Howard A. Baumer ,  Pieter Vorenkamp

IPC分类号： H04L7/00

CPC分类号： H04L7/0091 ,  H04L7/0025 ,  H04L7/0029 ,  H04L25/20

摘要： A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

摘要翻译： 提供了一种用于基于相位插值器的传输时钟控制的系统和方法。 该系统包括具有耦合到主定时发生器和传输模块的相位插值器的发射机。 相位插值器还耦合到接收器插值器控制模块和/或外部插值器控制模块。 当系统以重复模式运行时，发射机相位插值器从接收器插值器控制模块接收控制信号。 发射机相位内插器使用信号将传输时钟同步到采样时钟。 当系统在测试模式下操作时，用户在外部插值器控制模块中定义传输数据简档。 外部内插器控制模块基于轮廓生成控制信号。 发射机相位内插器使用该信号来生成传输模块使用的传输时钟，以生成具有所需简档的数据流。