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1.发明申请Fully digital transmitter including a digital band-pass sigma-delta modulator 有权全数字发射器，包括数字带通Σ-Δ调制器公开(公告)号：US20050265481A1
公开(公告)日：2005-12-01
申请号：US10856217
申请日：2004-05-28
CPC分类号： H04B1/0475 , H03F1/0205 , H03F1/223 , H03F2200/331 , H04L27/20
摘要： A digital transmitter (20) that may be advantageously used in a high-frequency transceiver, such as a wireless telephone handset, is disclosed. The transmitter (20) includes digital upconverter functions (36L, 36Q) that operate in combination with a digital band-pass sigma-delta modulator (40) to generate modulated digital signals at a sample frequency that is a multiple of the transmit frequency. The digital band-pass sigma-delta modulator (40) applies a noise transfer function in a feedback filter (72) in which the center of the pass band corresponds to the transmit frequency, and in which notches in the characteristic can be symmetrically or asymmetrically selected to correspond to specific frequencies, such as the receive band frequency, in which transmit noise is to be minimized. A combined FIR digital filter (42) and MOS power switch array (44) is also disclosed, in which a cascode arrangement of drain-extended MOS power transistors (78) and switching transistors (82) provide the output RF signal, with a coarse gain control (80) applied.
摘要翻译： 公开了一种可有利地用于诸如无线电话手机的高频收发器中的数字发射机（20）。 发射器（20）包括数字上变频器功能（36L，36Q），其与数字带通Σ-Δ调制器（40）组合工作，以产生调制数字信号，采样频率为发射频率的倍数 。 数字带通Σ-Δ调制器（40）在反馈滤波器（72）中应用噪声传递函数，其中通带的中心对应于发射频率，并且其中特性中的凹口可以对称或不对称地 被选择为对应于发射噪声将被最小化的特定频率，例如接收频带频率。 还公开了组合FIR数字滤波器（42）和MOS功率开关阵列（44），其中漏极扩展MOS功率晶体管（78）和开关晶体管（82）的共源共栅排列提供输出RF信号，粗略 增益控制（80）应用。
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公开(公告)号：US07376400B2
公开(公告)日：2008-05-20
申请号：US10915296
申请日：2004-08-10
CPC分类号： H04B1/30
摘要： A communications system comprising a processor, a variable oscillator, a radio frequency (RF) quadrature demodulator, a variable capacitor, a continuous-time, sigma-delta analog-to-digital converter (ADC), and a frequency divider, all integrated on a single semiconductor chip. The ADC samples the RF quadrature demodulator output. The processor sets the communications system frequency by controlling the oscillator, the frequency divider and the variable capacitor.
摘要翻译： 一种通信系统，包括处理器，可变振荡器，射频（RF）正交解调器，可变电容器，连续时间，Σ-Δ模数转换器（ADC）和分频器，所有这些都集成在 单个半导体芯片。 ADC采样RF正交解调器输出。 处理器通过控制振荡器，分频器和可变电容器来设置通信系统频率。
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3.发明授权Fully digital transmitter including a digital band-pass sigma-delta modulator 有权全数字发射器，包括数字带通Σ-Δ调制器公开(公告)号：US07061989B2
公开(公告)日：2006-06-13
申请号：US10856217
申请日：2004-05-28
CPC分类号： H04B1/0475 , H03F1/0205 , H03F1/223 , H03F2200/331 , H04L27/20
摘要： A digital transmitter (20) that may be advantageously used in a high-frequency transceiver, such as a wireless telephone handset, is disclosed. The transmitter (20) includes digital upconverter functions (36I, 36Q) that operate in combination with a digital band-pass sigma-delta modulator (40) to generate modulated digital signals at a sample frequency that is a multiple of the transmit frequency. The digital band-pass sigma-delta modulator (40) applies a noise transfer function in a feedback filter (72) in which the center of the pass band corresponds to the transmit frequency, and in which notches in the characteristic can be symmetrically or asymmetrically selected to correspond to specific frequencies, such as the receive band frequency, in which transmit noise is to be minimized. A combined FIR digital filter (42) and MOS power switch array (44) is also disclosed, in which a cascode arrangement of drain-extended MOS power transistors (78) and switching transistors (82) provide the output RF signal, with a coarse gain control (80) applied.
摘要翻译： 公开了一种可有利地用于诸如无线电话手机的高频收发器中的数字发射机（20）。 发射器（20）包括与数字带通Σ-Δ调制器（40）结合操作的数字上变频器功能（36 I，36 Q），以产生调制数字信号，采样频率为发射频率的倍数 。 数字带通Σ-Δ调制器（40）在反馈滤波器（72）中应用噪声传递函数，其中通带的中心对应于发射频率，并且其中特性中的凹口可以对称或不对称地 被选择为对应于发射噪声将被最小化的特定频率，例如接收频带频率。 还公开了组合FIR数字滤波器（42）和MOS功率开关阵列（44），其中漏极扩展MOS功率晶体管（78）和开关晶体管（82）的共源共栅排列提供输出RF信号，粗略 增益控制（80）应用。
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公开(公告)号：US20050070325A1
公开(公告)日：2005-03-31
申请号：US10915296
申请日：2004-08-10
CPC分类号： H04B1/30
摘要： A communications system comprising a processor, a variable oscillator, a radio frequency (RF) quadrature demodulator, a variable capacitor, a continuous-time, sigma-delta analog-to-digital converter (ADC), and a frequency divider, all integrated on a single semiconductor chip. The ADC samples the RF quadrature demodulator output. The processor sets the communications system frequency by controlling the oscillator, the frequency divider and the variable capacitor.
摘要翻译： 一种通信系统，包括处理器，可变振荡器，射频（RF）正交解调器，可变电容器，连续时间，Σ-Δ模数转换器（ADC）和分频器，所有这些都集成在 单个半导体芯片。 ADC采样RF正交解调器输出。 处理器通过控制振荡器，分频器和可变电容器来设置通信系统频率。
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5.发明申请Digital compensation of excess delay in continuous time sigma delta modulators 审中-公开连续时间Σ-Δ调制器的多余延迟的数字补偿公开(公告)号：US20050068213A1
公开(公告)日：2005-03-31
申请号：US10903608
申请日：2004-07-29
摘要： A continuous time sigma delta modulator having minimal excess loop delay. The continuous-time sigma delta modulator in accordance with the present invention includes at least one integrator stage coupled to receive an input signal and a resultant integrator output signal from a previous stage for providing a resultant integrator output. At least one output stage connects to the at least one integrator stage to receive the resultant integrator output signal from the previous integrator stage for providing a resultant integrator output. A sample and hold circuit connects to receive the second integrator input signal. A multiplier connects to the sample and hold circuit to provide a resultant sampled signal. An analog-to-digital converter quantizer couples to receive the resultant sampled signal and to produce a quantized output signal. A digital modulation loop circuit connects to the analog-to-digital converter quantizer to generate a resultant quantized output signal for correcting excess loop delay in the continuous time sigma delta modulator. A fourth feedback multiplier coupled to receive the resultant quantized output signal and produce a second resultant quantized output signal. A digital-to-analog converter coupled to receive the second resultant quantized output signal to produce a modulation feedback signal. A delay connects to the digital-to-analog converter to receive the modulation feedback signal and provide the resultant modulation feedback signal
摘要翻译： 具有最小多余循环延迟的连续时间Σ-Δ调制器。 根据本发明的连续时间Σ-Δ调制器包括至少一个积分器级，其被耦合以接收来自前一级的输入信号和合成积分器输出信号，以提供合成的积分器输出。 至少一个输出级连接到至少一个积分器级，以接收来自先前积分器级的合成积分器输出信号，以提供合成的积分器输出。 采样和保持电路连接以接收第二积分器输入信号。 乘法器连接到采样和保持电路以提供所得到的采样信号。 模拟 - 数字转换器量化器耦合以接收所得到的采样信号并产生量化的输出信号。 数字调制环电路连接到模数转换器量化器，以产生用于校正连续时间Σ-Δ调制器中的过多环路延迟的合成量化输出信号。 第四反馈乘法器耦合以接收所得到的量化输出信号并产生第二合成量化输出信号。 耦合以接收第二合成量化输出信号以产生调制反馈信号的数模转换器。 延迟连接到数模转换器以接收调制反馈信号并提供合成的调制反馈信号
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