公开(公告)号：US07701682B2

公开(公告)日：2010-04-20

申请号：US12023181

申请日：2008-01-31

申请人： Abhijat Goyal ,  Chai Ean E. Gill ,  James D. Whitfield

发明人： Abhijat Goyal ,  Chai Ean E. Gill ,  James D. Whitfield

IPC分类号： H02H9/00 ,  H02H3/22

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection device (61, 71), coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (41, 41′), each stage (41, 41′) comprising an interior node (52, 52′) and first (32, 32′) and second terminal (42, 42′) nodes wherein the first terminal node (42) of the first clamp stage (41) is coupled to the common terminal (23) and the second terminal node (42′) of the last clamp stages (41′) is coupled to the I/O terminals (22). A resistance-capacitance ladder (60) is provided in parallel with some of the clamp stages (41, 41′), with a resistance (R1, R2, R3 etc.) coupled to each of the nodes (32, 52, 65 (42; 32′)) of one of the ESD clamp stages (41, 41′) by first terminals thereof and capacitors (C1, C2, etc.) are coupled between second terminals of the resistances (R1, R2, R3 etc.). The clamp stages (41, 41′) are desirably bi-directional and a diode (D1) may bridge one or more of the clamp stages (e.g., 41) to provide different clamp voltages for different polarity ESD events.

摘要翻译： 一个静电放电（ESD）保护装置（61,71），耦合在芯片电路（24）的输入输出（I / O）（22）和公共（23）端子之间，以防止ESD事件， 包括多个串联的ESD钳位级（41,41'），每个级（41,41'）包括内部节点（52,52'）和第一（32,32'）和第二端子（42,42'）， 其中第一钳位级（41）的第一端子节点（42）耦合到公共端子（23）并且最后钳位级（41'）的第二端子节点（42'）耦合到I / O端子（22）。 电阻 - 电容梯（60）与一些钳位级（41,41'）并联设置，其中电阻（R1，R2，R3等）耦合到每个节点（32,52,65（ （R1，R2，R3等）的第二端子之间耦合电容器（C1，C2等）中的一个ESD钳位级（41,41'）的第一端， 。 钳位级（41,41'）希望是双向的，并且二极管（D1）可桥接一个或多个钳位级（例如41），以为不同极性的ESD事件提供不同的钳位电压。

公开(公告)号：US07911750B2

公开(公告)日：2011-03-22

申请号：US12038146

申请日：2008-02-27

申请人： Rouying Zhan ,  Chai Ean E. Gill ,  James D. Whitfield ,  Hongzhong Xu

发明人： Rouying Zhan ,  Chai Ean E. Gill ,  James D. Whitfield ,  Hongzhong Xu

IPC分类号： H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/86 ,  H01L29/87

摘要： An electrostatic discharge (ESD) protection device (41, 51, 61, 71, 81) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (41, 41′, 41″; 71, 71′, 71″), each stage (41, 41′, 41″; 71, 71′, 71″) comprising first (T1, T1′, T1″, etc.) and second transistors (T2, T2′, T2′″ etc.) having a common collector (52, 52′, 52″) and first (26, 26′, 26″) and second (36, 36′, 36″) emitters providing terminals (32, 42; 32′, 42′; 32″, 42″) of each clamp stage (41, 41′, 41″; 71, 71′, 71. A first emitter (25) of the first stage (41, 71) couples to the common terminal (23) and a second emitter (42″) of the last stage (41″, 71′) couples to the I/O terminals (22). Zener diode triggers are not used. Integrated external ESD trigger resistors (29, 29′, 29″; 39, 39′, 39″) (e.g., of poly SC) are coupled between the base (28, 28′, 28″; 38, 38′, 38″) and emitter (26, 26′, 26″; 36, 36′, 36″) of each transistor (T1, T1′, T1″; T2, T2′, T2″). Different resistor values (e.g., ˜0.5 k to 150 k Ohms) give different ESD trigger voltages. Cascading the clamp stages (41, 41′, 41″; 71, 71′) gives even higher trigger voltages. The ESD trigger resistances (29, 29′, 29″; 39, 39′, 39″) are desirably located outside the common collector-isolation wall (741, 742, 743; 741′, 742′, 743″) surrounding the transistors (T1, T1′, T1″; T2, T2′, T2″).

公开(公告)号：US08432654B2

公开(公告)日：2013-04-30

申请号：US13612466

申请日：2012-09-12

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

摘要翻译： 提供了耦合在受保护的半导体器件或集成电路的输入输出（I / O）和公共（GND）端子之间的静电放电（ESD）钳位。 一个ESD钳位包括源极 - 漏极耦合在GND和I / O端子之间的ESD晶体管（ESDT），耦合在栅极和源极之间的第一个电阻器和耦合在ESDT体和源极之间的第二个电阻器。 并联电阻器是控制晶体管，其栅极耦合到一个或多个偏置电源Vb，Vb'。 设备或IC的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。

公开(公告)号：US08279566B2

公开(公告)日：2012-10-02

申请号：US12112209

申请日：2008-04-30

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35′) with gates (38, 38′) coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT (25) during normal operation is much reduced.

摘要翻译： 被保护半导体SC器件的输入输出（I / O）（22）和公共（GND）（23）端子耦合的静电放电（ESD）钳位（41,41,61,71,81,91） IC（24）包括耦合在GND（23）和I / O（22）之间的源极 - 漏极（26,27）的ESD晶体管（ESDT）（25），耦合在栅极 28）和源极（26）以及耦合在ESDT体（29）和源极（26）之间的第二电阻器（30）。 并联电阻器（30,32）是与一个或多个偏置电源Vb，Vb'耦合的门（38,38'）的控制晶体管（35,35'）。 设备或IC（24）的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。 在正常运行期间通过ESDT（25）的寄生泄漏大大减少。

公开(公告)号：US20090273867A1

公开(公告)日：2009-11-05

申请号：US12112209

申请日：2008-04-30

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/04

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35′) with gates (38, 38′) coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT (25) during normal operation is much reduced.

摘要翻译： 被保护半导体SC器件的输入输出（I / O）（22）和公共（GND）（23）端子耦合的静电放电（ESD）钳位（41,41,61,71,81,91） IC（24）包括耦合在GND（23）和I / O（22）之间的源极 - 漏极（26,27）的ESD晶体管（ESDT）（25），耦合在栅极 28）和源极（26）和耦合在ESDT体（29）和源极（26）之间的第二电阻器（30）。 并联电阻器（30,32）是与一个或多个偏置电源Vb，Vb'耦合的门（38,38'）的控制晶体管（35,35'）。 设备或IC（24）的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。 在正常运行期间通过ESDT（25）的寄生泄漏大大减少。

公开(公告)号：US20130010394A1

公开(公告)日：2013-01-10

申请号：US13612466

申请日：2012-09-12

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/04

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

摘要翻译： 提供了耦合在受保护的半导体器件或集成电路的输入输出（I / O）和公共（GND）端子之间的静电放电（ESD）钳位。 一个ESD钳位包括源极 - 漏极耦合在GND和I / O端子之间的ESD晶体管（ESDT），耦合在栅极和源极之间的第一个电阻器和耦合在ESDT体和源极之间的第二个电阻器。 并联电阻器是控制晶体管，其栅极耦合到一个或多个偏置电源Vb，Vb'。 设备或IC的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。

公开(公告)号：US20090195944A1

公开(公告)日：2009-08-06

申请号：US12023181

申请日：2008-01-31

申请人： Abhijat Goyal ,  Chai Ean Gill ,  James D. Whitfield

发明人： Abhijat Goyal ,  Chai Ean Gill ,  James D. Whitfield

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection device (61, 71), coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (41, 41′), each stage (41, 41′) comprising an interior node (52, 52′) and first (32, 32′) and second terminal (42, 42′) nodes wherein the first terminal node (42) of the first clamp stage (41) is coupled to the common terminal (23) and the second terminal node (42′) of the last clamp stages (41′) is coupled to the I/O terminals (22). A resistance-capacitance ladder (60) is provided in parallel with some of the clamp stages (41, 41′), with a resistance (R1, R2, R3 etc.) coupled to each of the nodes (32, 52, 65 (42; 32′)) of one of the ESD clamp stages (41, 41′) by first terminals thereof and capacitors (C1, C2, etc.) are coupled between second terminals of the resistances (R1, R2, R3 etc.). The clamp stages (41, 41′) are desirably bi-directional and a diode (D1) may bridge one or more of the clamp stages (e.g., 41) to provide different clamp voltages for different polarity ESD events.

摘要翻译： 一个静电放电（ESD）保护装置（61,71），耦合在芯片电路（24）的输入输出（I / O）（22）和公共（23）端子之间，以防止ESD事件， 包括多个串联的ESD钳位级（41,41'），每个级（41,41'）包括内部节点（52,52'）和第一（32,32'）和第二端子（42,42'）， 其中第一钳位级（41）的第一端子节点（42）耦合到公共端子（23）并且最后钳位级（41'）的第二端子节点（42'）耦合到I / O端子（22）。 电阻 - 电容梯（60）与一些钳位级（41,41'）并联设置，其中电阻（R1，R2，R3等）耦合到每个节点（32,52,65（ （R1，R2，R3等）的第二端子之间耦合电容器（C1，C2等）中的一个ESD钳位级（41,41'）的第一端， 。 钳位级（41,41'）希望是双向的，并且二极管（D1）可桥接一个或多个钳位级（例如41），以为不同极性的ESD事件提供不同的钳位电压。

公开(公告)号：US07723823B2

公开(公告)日：2010-05-25

申请号：US12178800

申请日：2008-07-24

申请人： Chai Ean Gill ,  Changsoo Hong ,  James D. Whitfield ,  Rouying Zhan

发明人： Chai Ean Gill ,  Changsoo Hong ,  James D. Whitfield ,  Rouying Zhan

IPC分类号： H01L23/62

CPC分类号： H01L27/0259 ,  H01L29/735 ,  H01L29/861

摘要： An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that |Vt1TR−Vt1DC|˜0. This close matching increases the design margin and provides a higher performance ESD device (40) that is less sensitive to process variations, thereby improving manufacturing yield and reducing cost.

摘要翻译： 改进的侧向双极性静电放电（ESD）保护装置（40）包括半导体（SC）衬底（42），上覆外延SC层（44），发射极 - 集电区域（48,50），横向间隔开第一距离 （52），邻近所述发射极区域（48）的基极区域（54），所述基极区域（54）通过基极 - 集电极间隔（56）侧向朝向并且与所述集电极区域（50）分离，所述基极集电极间隔（56）被选择以设定所述期望的触发 电压Vt1。 通过在发射极区域（48）的下方设置一个掩埋层区域（49），所述掩埋层区域（49）与其集电极区域（50）的欧姆耦合，但不提供可比较的掩埋层区域（51），获得非对称结构，其中直流触发电压 （Vt1DC）和瞬态触发电压（Vt1TR）紧密匹配，使得| Vt1TR-Vt1DC | ~0。 这种紧密匹配增加了设计裕度，并提供了对工艺变化不那么敏感的更高性能的ESD器件（40），从而提高了制造产量并降低了成本。

公开(公告)号：US07074687B2

公开(公告)日：2006-07-11

申请号：US10407687

申请日：2003-04-04

申请人： James D. Whitfield

发明人： James D. Whitfield

IPC分类号： H01L21/336 ,  H01L21/331

CPC分类号： H01L27/0259 ,  H01L29/7322

摘要： An ESD protection device (20) comprises an N-type epitaxial collector (21), a first, lightly doped, deep base region (221) and second, highly doped, shallow base region (222) that extends a predetermined lateral dimension. The device responds to an ESD event by effecting vertical breakdown between the base regions and the N-type epitaxial collector. The ESD response is controlled by the predetermined lateral dimension, S, which, in one embodiment, may be is determined by a single masking step. Consequently, operation of the ESD protection device is rendered relatively insensitive to the tolerances of a fabrication process, and to variations between processes.

摘要翻译： ESD保护装置（20）包括N型外延收集器（21），第一轻掺杂深基区（221）和延伸预定横向尺寸的第二高掺杂浅基区（222）。 该器件通过在基极区域和N型外延收集器之间进行垂直击穿来响应ESD事件。 ESD响应由预定的横向尺寸S控制，S在一个实施例中可以由单个屏蔽步骤确定。 因此，ESD保护装置的操作对制造工艺的公差以及工艺之间的变化相对不敏感。

公开(公告)号：US20100244088A1

公开(公告)日：2010-09-30

申请号：US12415017

申请日：2009-03-31

申请人： James D. Whitfield ,  Changsoo Hong

发明人： James D. Whitfield ,  Changsoo Hong

IPC分类号： H01L27/06 ,  H01L21/8222

CPC分类号： H01L27/0259

摘要： Electrostatic discharge (ESD) protection clamps (61, 95) for I/O terminals (22, 23) of integrated circuit (IC) cores (24) comprise a bipolar transistor (25) with an integrated Zener diode (30) coupled between the base (28) and collector (27) of the transistor (25). Prior art variations (311, 312, 313, 314) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants (781, 782) and forming the base (28, 68) coupled anode (301, 75) and collector (27, 70, 64) coupled cathode (302, 72) of the Zener (30) using opposed edges (713, 714) of a single relatively thin mask (71, 71″). The anode (301, 75) and cathode (302, 72) are self-aligned and the width (691) of the Zener space charge region (69) therebetween is defined by the opposed edges (713, 714) substantially independent of location and orientation of the ESD clamps (61, 95) on the die or wafer. Because the mask (71, 71″) is relatively thin and the anode (301, 75) and cathode (302, 72) implants (781, 782) relatively shallow, mask shadowing is negligible and prior art clamp voltage variations (311, 312, 313, 314) are avoided.

摘要翻译： 集成电路（IC）核心（24）的I / O端子（22,23）的静电放电（ESD）保护夹具（61,95）包括双极晶体管（25），其具有集成齐纳二极管（30） 晶体管（25）的基极（28）和集电极（27）。 现有技术的变形（311,312,313,314）在现有技术的深植入物几何掩模阴影引起的同一IC芯片或晶片的不同部分中的钳位电压中，通过使用浅埋入（781,782）并形成基底 使用单个相对薄的掩模（71,74）的相对边缘（713,714）耦合阳极（301,75）和收集器（27,70,64）耦合的齐纳管（30）的阴极（302,72） 71“）。 阳极（301,75）和阴极（302,72）是自对准的，其间的齐纳空间电荷区域（69）的宽度（691）由基本上独立于位置的相对边缘（713,714）限定， ESD夹具（61,95）在模具或晶片上的取向。 由于掩模（71,71“）相对较薄并且阳极（301,75）和阴极（302,72）植入物（771,782）相对较浅，掩模阴影可忽略，现有技术的钳位电压变化（311,312 ，313,314）。