公开(公告)号：US07723823B2

公开(公告)日：2010-05-25

申请号：US12178800

申请日：2008-07-24

申请人： Chai Ean Gill ,  Changsoo Hong ,  James D. Whitfield ,  Rouying Zhan

发明人： Chai Ean Gill ,  Changsoo Hong ,  James D. Whitfield ,  Rouying Zhan

IPC分类号： H01L23/62

CPC分类号： H01L27/0259 ,  H01L29/735 ,  H01L29/861

摘要： An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that |Vt1TR−Vt1DC|˜0. This close matching increases the design margin and provides a higher performance ESD device (40) that is less sensitive to process variations, thereby improving manufacturing yield and reducing cost.

摘要翻译： 改进的侧向双极性静电放电（ESD）保护装置（40）包括半导体（SC）衬底（42），上覆外延SC层（44），发射极 - 集电区域（48,50），横向间隔开第一距离 （52），邻近所述发射极区域（48）的基极区域（54），所述基极区域（54）通过基极 - 集电极间隔（56）侧向朝向并且与所述集电极区域（50）分离，所述基极集电极间隔（56）被选择以设定所述期望的触发 电压Vt1。 通过在发射极区域（48）的下方设置一个掩埋层区域（49），所述掩埋层区域（49）与其集电极区域（50）的欧姆耦合，但不提供可比较的掩埋层区域（51），获得非对称结构，其中直流触发电压 （Vt1DC）和瞬态触发电压（Vt1TR）紧密匹配，使得| Vt1TR-Vt1DC | ~0。 这种紧密匹配增加了设计裕度，并提供了对工艺变化不那么敏感的更高性能的ESD器件（40），从而提高了制造产量并降低了成本。

公开(公告)号：US20120326206A1

公开(公告)日：2012-12-27

申请号：US13593608

申请日：2012-08-24

申请人： JAMES D. WHITFIELD ,  Changsoo Hong

发明人： JAMES D. WHITFIELD ,  Changsoo Hong

IPC分类号： H02H9/04

CPC分类号： H01L27/0259

摘要： Electrostatic discharge (ESD) protection clamps for I/O terminals of integrated circuit (IC) cores comprise a bipolar transistor with an integrated Zener diode coupled between the base and collector of the transistor. Variations in clamp voltage in different parts of the same IC chip or wafer caused by conventional deep implant geometric mask shadowing are avoided by using shallow implants and forming the base coupled anode and collector coupled cathode of the Zener using opposed edges of a single relatively thin mask. The anode and cathode are self-aligned, and the width of the Zener space charge region between them is defined by the opposed edges substantially independent of location and orientation of the ESD clamps on the die or wafer. Because the mask is relatively thin and the anode and cathode implants relatively shallow, mask shadowing is negligible and prior art clamp voltage variations are avoided.

摘要翻译： 集成电路（IC）内核的I / O端子的静电放电（ESD）保护钳包括一个双极晶体管，它具有耦合在晶体管的基极和集电极之间的集成齐纳二极管。 通过使用浅的植入物并且使用单个相对薄的掩模的相对边缘形成齐纳二极管的基极耦合的阳极和集电极耦合的阴极来避免由常规深度注入几何掩模阴影引起的同一IC芯片或晶片的不同部分中的钳位电压的变化 。 阳极和阴极是自对准的，并且它们之间的齐纳空间电荷区域的宽度由基本上独立于管芯或晶片上的ESD夹的位置和取向的相对边界限定。 因为掩模相对较薄并且阳极和阴极植入物相对浅，掩模阴影可忽略，并且避免了现有技术的钳位电压变化。

公开(公告)号：US20100244088A1

公开(公告)日：2010-09-30

申请号：US12415017

申请日：2009-03-31

申请人： James D. Whitfield ,  Changsoo Hong

发明人： James D. Whitfield ,  Changsoo Hong

IPC分类号： H01L27/06 ,  H01L21/8222

CPC分类号： H01L27/0259

摘要： Electrostatic discharge (ESD) protection clamps (61, 95) for I/O terminals (22, 23) of integrated circuit (IC) cores (24) comprise a bipolar transistor (25) with an integrated Zener diode (30) coupled between the base (28) and collector (27) of the transistor (25). Prior art variations (311, 312, 313, 314) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants (781, 782) and forming the base (28, 68) coupled anode (301, 75) and collector (27, 70, 64) coupled cathode (302, 72) of the Zener (30) using opposed edges (713, 714) of a single relatively thin mask (71, 71″). The anode (301, 75) and cathode (302, 72) are self-aligned and the width (691) of the Zener space charge region (69) therebetween is defined by the opposed edges (713, 714) substantially independent of location and orientation of the ESD clamps (61, 95) on the die or wafer. Because the mask (71, 71″) is relatively thin and the anode (301, 75) and cathode (302, 72) implants (781, 782) relatively shallow, mask shadowing is negligible and prior art clamp voltage variations (311, 312, 313, 314) are avoided.

摘要翻译： 集成电路（IC）核心（24）的I / O端子（22,23）的静电放电（ESD）保护夹具（61,95）包括双极晶体管（25），其具有集成齐纳二极管（30） 晶体管（25）的基极（28）和集电极（27）。 现有技术的变形（311,312,313,314）在现有技术的深植入物几何掩模阴影引起的同一IC芯片或晶片的不同部分中的钳位电压中，通过使用浅埋入（781,782）并形成基底 使用单个相对薄的掩模（71,74）的相对边缘（713,714）耦合阳极（301,75）和收集器（27,70,64）耦合的齐纳管（30）的阴极（302,72） 71“）。 阳极（301,75）和阴极（302,72）是自对准的，其间的齐纳空间电荷区域（69）的宽度（691）由基本上独立于位置的相对边缘（713,714）限定， ESD夹具（61,95）在模具或晶片上的取向。 由于掩模（71,71“）相对较薄并且阳极（301,75）和阴极（302,72）植入物（771,782）相对较浅，掩模阴影可忽略，现有技术的钳位电压变化（311,312 ，313,314）。

公开(公告)号：US20100019341A1

公开(公告)日：2010-01-28

申请号：US12178800

申请日：2008-07-24

申请人： Chai Ean Gill ,  Changsoo Hong ,  James D. Whitfield ,  Rouying Zhan

发明人： Chai Ean Gill ,  Changsoo Hong ,  James D. Whitfield ,  Rouying Zhan

IPC分类号： H01L23/62

CPC分类号： H01L27/0259 ,  H01L29/735 ,  H01L29/861

摘要： An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that ∥Vt1TR−Vt1DC∥˜0. This close matching increases the design margin and provides a higher performance ESD device (40) that is less sensitive to process variations, thereby improving manufacturing yield and reducing cost.

摘要翻译： 改进的侧向双极性静电放电（ESD）保护装置（40）包括半导体（SC）衬底（42），上覆外延SC层（44），发射极 - 集电区域（48,50），横向间隔开第一距离 （52），邻近所述发射极区域（48）的基极区域（54），所述基极区域（54）通过基极 - 集电极间隔（56）侧向朝向并且与所述集电极区域（50）分离，所述基极集电极间隔（56）被选择以设定所述期望的触发 电压Vt1。 通过在发射极区域（48）的下方设置一个掩埋层区域（49），所述掩埋层区域（49）与其集电极区域（50）的欧姆耦合，但不提供可比较的掩埋层区域（51），获得非对称结构，其中直流触发电压 （Vt1DC）和瞬态触发电压（Vt1TR）紧密匹配，使得‖Vt1TR-Vt1DC‖〜0。 这种紧密匹配增加了设计裕度，并提供了对工艺变化不那么敏感的更高性能的ESD器件（40），从而提高了制造产量并降低了成本。

公开(公告)号：US08531005B2

公开(公告)日：2013-09-10

申请号：US13593608

申请日：2012-08-24

申请人： James D. Whitfield ,  Changsoo Hong

发明人： James D. Whitfield ,  Changsoo Hong

IPC分类号： H01L29/866

CPC分类号： H01L27/0259

摘要： Electrostatic discharge (ESD) protection clamps for I/O terminals of integrated circuit (IC) cores comprise a bipolar transistor with an integrated Zener diode coupled between the base and collector of the transistor. Variations in clamp voltage in different parts of the same IC chip or wafer caused by conventional deep implant geometric mask shadowing are avoided by using shallow implants and forming the base coupled anode and collector coupled cathode of the Zener using opposed edges of a single relatively thin mask. The anode and cathode are self-aligned, and the width of the Zener space charge region between them is defined by the opposed edges substantially independent of location and orientation of the ESD clamps on the die or wafer. Because the mask is relatively thin and the anode and cathode implants relatively shallow, mask shadowing is negligible and prior art clamp voltage variations are avoided.

摘要翻译： 集成电路（IC）内核的I / O端子的静电放电（ESD）保护钳包括一个双极晶体管，它具有耦合在晶体管的基极和集电极之间的集成齐纳二极管。 通过使用浅的植入物并且使用单个相对薄的掩模的相对边缘形成齐纳二极管的基极耦合的阳极和集电极耦合的阴极来避免由常规深度注入几何掩模阴影引起的同一IC芯片或晶片的不同部分中的钳位电压的变化 。 阳极和阴极是自对准的，并且它们之间的齐纳空间电荷区域的宽度由基本上独立于管芯或晶片上的ESD夹的位置和取向的相对边界限定。 因为掩模相对较薄并且阳极和阴极植入物相对浅，掩模阴影可忽略，并且避免了现有技术的钳位电压变化。

公开(公告)号：US08252656B2

公开(公告)日：2012-08-28

申请号：US12415017

申请日：2009-03-31

申请人： James D. Whitfield ,  Changsoo Hong

发明人： James D. Whitfield ,  Changsoo Hong

IPC分类号： H01L21/8222 ,  H01L21/426

CPC分类号： H01L27/0259

摘要： Electrostatic discharge (ESD) protection clamps (61, 95) for I/O terminals (22, 23) of integrated circuit (IC) cores (24) comprise a bipolar transistor (25) with an integrated Zener diode (30) coupled between the base (28) and collector (27) of the transistor (25). Prior art variations (311, 312, 313, 314) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants (781, 782) and forming the base (28, 68) coupled anode (301, 75) and collector (27, 70, 64) coupled cathode (302, 72) of the Zener (30) using opposed edges (713, 714) of a single relatively thin mask (71, 71″). The anode (301, 75) and cathode (302, 72) are self-aligned and the width (691) of the Zener space charge region (69) therebetween is defined by the opposed edges (713, 714) substantially independent of location and orientation of the ESD clamps (61, 95) on the die or wafer. Because the mask (71, 71″) is relatively thin and the anode (301, 75) and cathode (302, 72) implants (781, 782) relatively shallow, mask shadowing is negligible and prior art clamp voltage variations (311, 312, 313, 314) are avoided.

摘要翻译： 集成电路（IC）核心（24）的I / O端子（22,23）的静电放电（ESD）保护夹具（61,95）包括双极晶体管（25），其具有集成齐纳二极管（30） 晶体管（25）的基极（28）和集电极（27）。 现有技术的变形（311,312,313,314）在现有技术的深植入物几何掩模阴影引起的同一IC芯片或晶片的不同部分中的钳位电压中，通过使用浅埋入（781,782）并形成基底 使用单个相对薄的掩模（71,74）的相对边缘（713,714）耦合阳极（301,75）和收集器（27,70,64）耦合的齐纳管（30）的阴极（302,72） 71“）。 阳极（301,75）和阴极（302,72）是自对准的，其间的齐纳空间电荷区域（69）的宽度（691）由基本上独立于位置的相对边缘（713,714）限定， ESD夹具（61,95）在模具或晶片上的取向。 由于掩模（71,71“）相对较薄并且阳极（301,75）和阴极（302,72）植入物（771,782）相对较浅，掩模阴影可忽略，现有技术的钳位电压变化（311,312 ，313,314）。

公开(公告)号：US20140225156A1

公开(公告)日：2014-08-14

申请号：US13764523

申请日：2013-02-11

申请人： Rouying Zhan ,  Chai Ean Gill ,  William G. Cowden ,  Changsoo Hong

发明人： Rouying Zhan ,  Chai Ean Gill ,  William G. Cowden ,  Changsoo Hong

IPC分类号： H01L27/02 ,  H01L29/66 ,  H01L29/73

CPC分类号： H01L29/73 ,  H01L27/0277 ,  H01L29/0653 ,  H01L29/66325 ,  H01L29/735 ,  H01L29/7835

摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to shunt ESD discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs.

摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，半导体衬底中的基极区域，具有第一导电类型，基极区域中的发射极区域，具有第二导电类型，半导体衬底中的集电极区域间隔开 具有第二导电类型的具有第二导电类型的击穿触发区域横向设置在基极区域和集电极区域之间以限定发生击穿的结，以触发ESD保护装置以分流ESD放电 电流以及由击穿触发区域上的半导体衬底支撑并电连接到基极区域和发射极区域的栅极结构。 击穿触发区域的横向宽度被配置成建立发生击穿的电压电平。

公开(公告)号：US09583603B2

公开(公告)日：2017-02-28

申请号：US13764523

申请日：2013-02-11

申请人： Rouying Zhan ,  Chai Ean Gill ,  William G. Cowden ,  Changsoo Hong

发明人： Rouying Zhan ,  Chai Ean Gill ,  William G. Cowden ,  Changsoo Hong

IPC分类号： H01L29/73 ,  H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/735 ,  H01L29/06

CPC分类号： H01L29/73 ,  H01L27/0277 ,  H01L29/0653 ,  H01L29/66325 ,  H01L29/735 ,  H01L29/7835

摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to shunt ESD discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs.

摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，半导体衬底中的基极区域，具有第一导电类型，基极区域中的发射极区域，具有第二导电类型，半导体衬底中的集电极区域间隔开 具有第二导电类型的具有第二导电类型的击穿触发区域横向设置在基极区域和集电极区域之间以限定发生击穿的结，以触发ESD保护装置以分流ESD放电 电流以及由击穿触发区域上的半导体衬底支撑并电连接到基极区域和发射极区域的栅极结构。 击穿触发区域的横向宽度被配置为建立发生击穿的电压电平。

公开(公告)号：US08994068B2

公开(公告)日：2015-03-31

申请号：US13599244

申请日：2012-08-30

申请人： Rouying Zhan ,  Chai E Gill ,  Changsoo Hong

发明人： Rouying Zhan ,  Chai E Gill ,  Changsoo Hong

IPC分类号： H01L29/66 ,  H01L23/62 ,  H01L27/02 ,  H01L21/425 ,  H01L29/87

CPC分类号： H01L29/87 ,  H01L27/0262

摘要： An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate. The first electrostatic discharge protection device includes a buried layer formed over the substrate, the buried layer having a first conductivity type and defining an opening located over a region of the substrate, a first transistor formed over the opening of the buried layer, the first transistor having an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp, and a second transistor formed over the buried layer, the second transistor having an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp.

摘要翻译： 本发明提供了一种静电放电保护钳，其适用于限制出现在静电放电保护钳耦合到的集成电路的受保护端子上的电压。 静电放电保护夹具包括衬底和形成在衬底上的第一静电放电保护器件。 第一静电放电保护器件包括形成在衬底上的掩埋层，所述掩埋层具有第一导电类型并且限定位于衬底的区域上方的开口，形成在掩埋层的开口上的第一晶体管，第一晶体管 具有耦合到所述静电放电保护钳位件的第一阴极端子的发射极和形成在所述掩埋层上的第二晶体管，所述第二晶体管具有耦合到所述静电放电保护钳位件的第一阳极端子的发射极。

公开(公告)号：US09786652B2

公开(公告)日：2017-10-10

申请号：US14854366

申请日：2015-09-15

申请人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

IPC分类号： H01L29/74 ,  H01L29/747 ,  H01L29/00 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L27/02 ,  H01L29/66 ,  H01L23/60 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/082 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/73 ,  H01L29/7317 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.