公开(公告)号：US08432654B2

公开(公告)日：2013-04-30

申请号：US13612466

申请日：2012-09-12

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

摘要翻译： 提供了耦合在受保护的半导体器件或集成电路的输入输出（I / O）和公共（GND）端子之间的静电放电（ESD）钳位。 一个ESD钳位包括源极 - 漏极耦合在GND和I / O端子之间的ESD晶体管（ESDT），耦合在栅极和源极之间的第一个电阻器和耦合在ESDT体和源极之间的第二个电阻器。 并联电阻器是控制晶体管，其栅极耦合到一个或多个偏置电源Vb，Vb'。 设备或IC的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。

公开(公告)号：US20090273867A1

公开(公告)日：2009-11-05

申请号：US12112209

申请日：2008-04-30

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/04

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35′) with gates (38, 38′) coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT (25) during normal operation is much reduced.

摘要翻译： 被保护半导体SC器件的输入输出（I / O）（22）和公共（GND）（23）端子耦合的静电放电（ESD）钳位（41,41,61,71,81,91） IC（24）包括耦合在GND（23）和I / O（22）之间的源极 - 漏极（26,27）的ESD晶体管（ESDT）（25），耦合在栅极 28）和源极（26）和耦合在ESDT体（29）和源极（26）之间的第二电阻器（30）。 并联电阻器（30,32）是与一个或多个偏置电源Vb，Vb'耦合的门（38,38'）的控制晶体管（35,35'）。 设备或IC（24）的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。 在正常运行期间通过ESDT（25）的寄生泄漏大大减少。

公开(公告)号：US08279566B2

公开(公告)日：2012-10-02

申请号：US12112209

申请日：2008-04-30

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35′) with gates (38, 38′) coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT (25) during normal operation is much reduced.

摘要翻译： 被保护半导体SC器件的输入输出（I / O）（22）和公共（GND）（23）端子耦合的静电放电（ESD）钳位（41,41,61,71,81,91） IC（24）包括耦合在GND（23）和I / O（22）之间的源极 - 漏极（26,27）的ESD晶体管（ESDT）（25），耦合在栅极 28）和源极（26）以及耦合在ESDT体（29）和源极（26）之间的第二电阻器（30）。 并联电阻器（30,32）是与一个或多个偏置电源Vb，Vb'耦合的门（38,38'）的控制晶体管（35,35'）。 设备或IC（24）的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。 在正常运行期间通过ESDT（25）的寄生泄漏大大减少。

公开(公告)号：US20130010394A1

公开(公告)日：2013-01-10

申请号：US13612466

申请日：2012-09-12

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/04

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

摘要翻译： 提供了耦合在受保护的半导体器件或集成电路的输入输出（I / O）和公共（GND）端子之间的静电放电（ESD）钳位。 一个ESD钳位包括源极 - 漏极耦合在GND和I / O端子之间的ESD晶体管（ESDT），耦合在栅极和源极之间的第一个电阻器和耦合在ESDT体和源极之间的第二个电阻器。 并联电阻器是控制晶体管，其栅极耦合到一个或多个偏置电源Vb，Vb'。 设备或IC的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。

公开(公告)号：US20090195944A1

公开(公告)日：2009-08-06

申请号：US12023181

申请日：2008-01-31

申请人： Abhijat Goyal ,  Chai Ean Gill ,  James D. Whitfield

发明人： Abhijat Goyal ,  Chai Ean Gill ,  James D. Whitfield

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection device (61, 71), coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (41, 41′), each stage (41, 41′) comprising an interior node (52, 52′) and first (32, 32′) and second terminal (42, 42′) nodes wherein the first terminal node (42) of the first clamp stage (41) is coupled to the common terminal (23) and the second terminal node (42′) of the last clamp stages (41′) is coupled to the I/O terminals (22). A resistance-capacitance ladder (60) is provided in parallel with some of the clamp stages (41, 41′), with a resistance (R1, R2, R3 etc.) coupled to each of the nodes (32, 52, 65 (42; 32′)) of one of the ESD clamp stages (41, 41′) by first terminals thereof and capacitors (C1, C2, etc.) are coupled between second terminals of the resistances (R1, R2, R3 etc.). The clamp stages (41, 41′) are desirably bi-directional and a diode (D1) may bridge one or more of the clamp stages (e.g., 41) to provide different clamp voltages for different polarity ESD events.

摘要翻译： 一个静电放电（ESD）保护装置（61,71），耦合在芯片电路（24）的输入输出（I / O）（22）和公共（23）端子之间，以防止ESD事件， 包括多个串联的ESD钳位级（41,41'），每个级（41,41'）包括内部节点（52,52'）和第一（32,32'）和第二端子（42,42'）， 其中第一钳位级（41）的第一端子节点（42）耦合到公共端子（23）并且最后钳位级（41'）的第二端子节点（42'）耦合到I / O端子（22）。 电阻 - 电容梯（60）与一些钳位级（41,41'）并联设置，其中电阻（R1，R2，R3等）耦合到每个节点（32,52,65（ （R1，R2，R3等）的第二端子之间耦合电容器（C1，C2等）中的一个ESD钳位级（41,41'）的第一端， 。 钳位级（41,41'）希望是双向的，并且二极管（D1）可桥接一个或多个钳位级（例如41），以为不同极性的ESD事件提供不同的钳位电压。

公开(公告)号：US07701682B2

公开(公告)日：2010-04-20

申请号：US12023181

申请日：2008-01-31

申请人： Abhijat Goyal ,  Chai Ean E. Gill ,  James D. Whitfield

发明人： Abhijat Goyal ,  Chai Ean E. Gill ,  James D. Whitfield

IPC分类号： H02H9/00 ,  H02H3/22

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection device (61, 71), coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (41, 41′), each stage (41, 41′) comprising an interior node (52, 52′) and first (32, 32′) and second terminal (42, 42′) nodes wherein the first terminal node (42) of the first clamp stage (41) is coupled to the common terminal (23) and the second terminal node (42′) of the last clamp stages (41′) is coupled to the I/O terminals (22). A resistance-capacitance ladder (60) is provided in parallel with some of the clamp stages (41, 41′), with a resistance (R1, R2, R3 etc.) coupled to each of the nodes (32, 52, 65 (42; 32′)) of one of the ESD clamp stages (41, 41′) by first terminals thereof and capacitors (C1, C2, etc.) are coupled between second terminals of the resistances (R1, R2, R3 etc.). The clamp stages (41, 41′) are desirably bi-directional and a diode (D1) may bridge one or more of the clamp stages (e.g., 41) to provide different clamp voltages for different polarity ESD events.

摘要翻译： 一个静电放电（ESD）保护装置（61,71），耦合在芯片电路（24）的输入输出（I / O）（22）和公共（23）端子之间，以防止ESD事件， 包括多个串联的ESD钳位级（41,41'），每个级（41,41'）包括内部节点（52,52'）和第一（32,32'）和第二端子（42,42'）， 其中第一钳位级（41）的第一端子节点（42）耦合到公共端子（23）并且最后钳位级（41'）的第二端子节点（42'）耦合到I / O端子（22）。 电阻 - 电容梯（60）与一些钳位级（41,41'）并联设置，其中电阻（R1，R2，R3等）耦合到每个节点（32,52,65（ （R1，R2，R3等）的第二端子之间耦合电容器（C1，C2等）中的一个ESD钳位级（41,41'）的第一端， 。 钳位级（41,41'）希望是双向的，并且二极管（D1）可桥接一个或多个钳位级（例如41），以为不同极性的ESD事件提供不同的钳位电压。

公开(公告)号：US07814776B2

公开(公告)日：2010-10-19

申请号：US11719120

申请日：2005-11-10

申请人： Peter C. Eklund ,  Abhijat Goyal ,  Srinivas A. Tadigadapa

发明人： Peter C. Eklund ,  Abhijat Goyal ,  Srinivas A. Tadigadapa

IPC分类号： G01N29/02

CPC分类号： B82Y30/00 ,  B82Y15/00 ,  G01N27/06 ,  G01N29/022 ,  G01N29/036 ,  G01N2291/0212 ,  G01N2291/0215 ,  G01N2291/0237 ,  G01N2291/0256 ,  G01N2291/02863 ,  G01N2291/0422 ,  G01N2291/0423 ,  G01N2291/0426 ,  G01N2291/0427 ,  G01N2291/101

摘要： Methods for sensing and building sensors provide for adding nanotubes to a sensor to improve characteristics such as the Q-factor associated with the sensor. Mass loading and damping characteristics of micromachined quartz crystal resonators on which a thin film of debundled single-walled carbon nanotube (SWNT) has been deposited are disclosed. An absolute mass sensitivity of ˜100 fg was experimentally measured by monitoring the continuous desorption of gases from SWNT surfaces in a vacuum ambient.

摘要翻译： 用于感测和构建传感器的方法提供了向传感器添加纳米管以改善诸如与传感器相关联的Q因子的特性。 公开了其上已经沉积有分解的单层碳纳米管（SWNT）的薄膜的微加工石英晶体谐振器的质量负载和阻尼特性。 通过在真空环境中监测来自SWNT表面的气体的连续解吸，实验测量了约100fg的绝对质量灵敏度。

公开(公告)号：US20090145233A1

公开(公告)日：2009-06-11

申请号：US11719120

申请日：2005-11-10

申请人： Peter C. Eklund ,  Abhijat Goyal ,  Srinivas A. Tadigadapa

发明人： Peter C. Eklund ,  Abhijat Goyal ,  Srinivas A. Tadigadapa

IPC分类号： G01H11/00

CPC分类号： B82Y30/00 ,  B82Y15/00 ,  G01N27/06 ,  G01N29/022 ,  G01N29/036 ,  G01N2291/0212 ,  G01N2291/0215 ,  G01N2291/0237 ,  G01N2291/0256 ,  G01N2291/02863 ,  G01N2291/0422 ,  G01N2291/0423 ,  G01N2291/0426 ,  G01N2291/0427 ,  G01N2291/101

摘要： Methods for sensing and building sensors provide for adding nanotubes to a sensor to improve characteristics such as the Q-factor associated with the sensor. Mass loading and damping characteristics of micromachined quartz crystal resonators on which a thin film of debundled single-walled carbon nanotube (SWNT) has been deposited are disclosed. An absolute mass sensitivity of ˜100 fg was experimentally measured by monitoring the continuous desorption of gases from SWNT surfaces in a vacuum ambient.

摘要翻译： 用于感测和构建传感器的方法提供了向传感器添加纳米管以改善诸如与传感器相关联的Q因子的特性。 公开了其上已经沉积有分解的单层碳纳米管（SWNT）的薄膜的微加工石英晶体谐振器的质量负载和阻尼特性。 通过在真空环境中监测来自SWNT表面的气体的连续解吸，实验测量了约100fg的绝对质量灵敏度。