3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME
    1.
    发明申请
    3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME 有权
    具有低接触电阻的3D多晶硅二极管及其形成方法

    公开(公告)号:US20110062557A1

    公开(公告)日:2011-03-17

    申请号:US12562079

    申请日:2009-09-17

    IPC分类号: H01L29/868 H01L21/329

    摘要: A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

    摘要翻译: 半导体p-i-n二极管及其形成方法在此描述。 在一个方面,在被掺杂为具有一个导电性(p +或n +)和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻,这可能增加正向偏置电流。 掺杂区域延伸到SiGe区域的下方,使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加,这是由于添加的SiGe区域的结果。 在一个实施例中,SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配,其可以在这些二极管与 3D存储器阵列中的R / W材料。

    3D polysilicon diode with low contact resistance and method for forming same
    2.
    发明授权
    3D polysilicon diode with low contact resistance and method for forming same 有权
    具有低接触电阻的3D多晶硅二极管及其形成方法

    公开(公告)号:US08410582B2

    公开(公告)日:2013-04-02

    申请号:US13479093

    申请日:2012-05-23

    IPC分类号: H01L29/66

    摘要: A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

    摘要翻译: 半导体p-i-n二极管及其形成方法在此描述。 在一个方面,在被掺杂为具有一个导电性(p +或n +)和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻,这可能增加正向偏置电流。 掺杂区域延伸到SiGe区域的下方,使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加,这是由于添加的SiGe区域的结果。 在一个实施例中,SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配,其可以在这些二极管与 3D存储器阵列中的R / W材料。

    DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME
    3.
    发明申请
    DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME 有权
    具有用于存储器阵列的内部氧化物区域的二极体及其形成方法

    公开(公告)号:US20120193756A1

    公开(公告)日:2012-08-02

    申请号:US13020007

    申请日:2011-02-02

    摘要: In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.

    摘要翻译: 在第一方面,提供一种垂直半导体二极管,其包括:(1)形成在基板上的第一半导体层; (2)形成在第一半导体层上方的第二半导体层; (3)形成在所述第一半导体层上方的第一自然氧化物层; 以及(4)形成在第一半导体层上的第三半导体层,第二半导体层和第一自然氧化物层,以形成包括第一自然氧化物层的垂直半导体二极管。 提供了许多其他方面。

    3D polysilicon diode with low contact resistance and method for forming same
    4.
    发明授权
    3D polysilicon diode with low contact resistance and method for forming same 有权
    具有低接触电阻的3D多晶硅二极管及其形成方法

    公开(公告)号:US08207064B2

    公开(公告)日:2012-06-26

    申请号:US12562079

    申请日:2009-09-17

    IPC分类号: H01L21/44

    摘要: A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

    摘要翻译: 半导体p-i-n二极管及其形成方法在此描述。 在一个方面,在被掺杂为具有一个导电性(p +或n +)和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻,这可能增加正向偏置电流。 掺杂区域延伸到SiGe区域的下方,使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加,这是由于添加的SiGe区域的结果。 在一个实施例中,SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配,其可以在这些二极管与 3D存储器阵列中的R / W材料。

    Diodes with native oxide regions for use in memory arrays and methods of forming the same
    5.
    发明授权
    Diodes with native oxide regions for use in memory arrays and methods of forming the same 有权
    具有用于存储器阵列的自然氧化物区域的二极管及其形成方法

    公开(公告)号:US08866124B2

    公开(公告)日:2014-10-21

    申请号:US13020007

    申请日:2011-02-02

    摘要: In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.

    摘要翻译: 在第一方面,提供一种垂直半导体二极管,其包括:(1)形成在基板上的第一半导体层; (2)形成在第一半导体层上方的第二半导体层; (3)形成在所述第一半导体层上方的第一自然氧化物层; 以及(4)形成在第一半导体层上的第三半导体层,第二半导体层和第一自然氧化物层,以形成包括第一自然氧化物层的垂直半导体二极管。 提供了许多其他方面。

    3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME
    6.
    发明申请
    3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME 有权
    具有低接触电阻的3D多晶硅二极管及其形成方法

    公开(公告)号:US20120228579A1

    公开(公告)日:2012-09-13

    申请号:US13479093

    申请日:2012-05-23

    IPC分类号: H01L27/10 H01L21/329

    摘要: A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

    摘要翻译: 半导体p-i-n二极管及其形成方法在此描述。 在一个方面,在被掺杂为具有一个导电性(p +或n +)和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻,这可能增加正向偏置电流。 掺杂区域延伸到SiGe区域的下方,使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加,这是由于添加的SiGe区域的结果。 在一个实施例中,SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配,其可以在这些二极管与 3D存储器阵列中的R / W材料。