公开(公告)号：US08984470B2

公开(公告)日：2015-03-17

申请号：US12608446

申请日：2009-10-29

申请人： Abhijit Chakanakar ,  Tong Gao

发明人： Abhijit Chakanakar ,  Tong Gao

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/72

摘要： One embodiment of the present invention provides a system that concurrently performs redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design. During operation, the system performs an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias. The system then performs a redundant-via-insertion operation on the routing solution, wherein the redundant-via-insertion operation attempts to modify a via within the set of vias into a redundant via. Next, the system performs a timing optimization on the routing solution by iteratively: (1) performing a timing analysis on the routing solution; (2) performing a logic optimization on the routing solution; and (3) performing an incremental routing adjustment on the routing solution, wherein the incremental routing adjustment adjusts the redundant vias.

摘要翻译： 本发明的一个实施例提供了一种在集成电路（IC）芯片设计的路由期间同时执行冗余通过插入和定时优化的系统。 在运行期间，系统在IC芯片设计上执行初始路由以获得路由解决方案，其中包括一组过孔。 然后，系统对路由解决方案执行冗余通过插入操作，其中冗余通过插入操作尝试将该组通孔内的通道修改为冗余通路。 接下来，系统通过迭代地对路由解决方案进行定时优化：（1）对路由解决方案执行定时分析; （2）对路由解决方案执行逻辑优化; 以及（3）对所述路由解决方案执行增量路由调整，其中所述增量路由调整调整所述冗余通路。

公开(公告)号：US20110055785A1

公开(公告)日：2011-03-03

申请号：US12608446

申请日：2009-10-29

申请人： Abhijit Chakanakar ,  Tong Gao

发明人： Abhijit Chakanakar ,  Tong Gao

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/72

摘要： One embodiment of the present invention provides a system that concurrently performs redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design. During operation, the system performs an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias. The system then performs a redundant-via-insertion operation on the routing solution, wherein the redundant-via-insertion operation attempts to modify a via within the set of vias into a redundant via. Next, the system performs a timing optimization on the routing solution by iteratively: (1) performing a timing analysis on the routing solution; (2) performing a logic optimization on the routing solution; and (3) performing an incremental routing adjustment on the routing solution, wherein the incremental routing adjustment adjusts the redundant vias.

摘要翻译： 本发明的一个实施例提供了一种在集成电路（IC）芯片设计的路由期间同时执行冗余通过插入和定时优化的系统。 在运行期间，系统在IC芯片设计上执行初始路由以获得路由解决方案，其中包括一组过孔。 然后，系统对路由解决方案执行冗余通过插入操作，其中冗余通过插入操作尝试将该组通孔内的通道修改为冗余通路。 接下来，系统通过迭代地对路由解决方案进行定时优化：（1）对路由解决方案执行定时分析; （2）对路由解决方案进行逻辑优化; 以及（3）对所述路由解决方案执行增量路由调整，其中所述增量路由调整调整所述冗余通路。

公开(公告)号：US20110185329A1

公开(公告)日：2011-07-28

申请号：US12695513

申请日：2010-01-28

申请人： Linni Wen ,  Tong Gao

发明人： Linni Wen ,  Tong Gao

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Some embodiments of the present invention provide systems for generating and using a route fix guidance for fixing design rule violations. A route fix guidance includes information that enables a router to locally modify a routing solution to fix one or more design rule violations. A route fix guidance can include a set of two or more metal avoidance areas, wherein avoiding any one of the set of two or more metal avoidance areas during routing fixes the design rule violation. Additionally, a route fix guidance can specify a set of rectangles to remove from a routing solution, and a set of rectangles to insert into or add to a routing solution. Further, the route fix guidance can include information for moving one or more vias to new locations in the routing solution. The route fix guidance can specify a sequence in which the local modifications are to be made.

摘要翻译： 本发明的一些实施例提供用于生成和使用用于固定设计规则违规的路线固定引导的系统。 路由修复指南包括使路由器能够本地修改路由解决方案以修复一个或多个设计规则违规的信息。 路线固定引导件可以包括一组两个或多个金属回避区域，其中在路由期间避免该组两个或多个金属回避区域中的任何一个固定了设计规则违规。 另外，路由修复引导可以指定要从路由解决方案中移除的一组矩形以及一组插入或添加到路由解决方案中的矩形。 此外，路线修复引导可以包括用于将一个或多个通孔移动到路由解决方案中的新位置的信息。 路线修复指导可以指定要进行局部修改的顺序。

公开(公告)号：US20080293317A1

公开(公告)日：2008-11-27

申请号：US11629006

申请日：2005-06-20

申请人： Antonio Batistini ,  Tong Gao ,  Jerry C.T. Wang

发明人： Antonio Batistini ,  Tong Gao ,  Jerry C.T. Wang

IPC分类号： B32B5/02

CPC分类号： D06M15/263 ,  D03D15/08 ,  D06M13/127 ,  D06M13/285 ,  D06M2200/20 ,  Y10T442/2393

摘要： The present disclosure is directed to stretch or elastic textile articles having wrinkle resistance. The textile articles are preferably cellulosic, more preferably cotton-based. The stretch levels for these articles is preferably greater than about 8 percent and preferably have a DP rating (as determined according to AATCC 143-1996 or AATCC 124-2001) of at least 3.0.

摘要翻译： 本公开涉及具有抗皱性的拉伸或弹性织物制品。 纺织制品优选纤维素，更优选棉基。 这些制品的拉伸水平优选大于约8％，优选具有至少3.0的DP等级（根据AATCC 143-1996或AATCC 124-2001确定）。

公开(公告)号：US06286128B1

公开(公告)日：2001-09-04

申请号：US09097299

申请日：1998-06-12

申请人： Lawrence Pileggi ,  Majid Sarrafzadeh ,  Sharad Malik ,  Abhijeet Chakraborty ,  Archie Li ,  Robert Eugene Shortt ,  Christopher Dunn ,  David Gluss ,  Dennis Yamamoto ,  Dinesh Gaitonde ,  Douglas B. Boyle ,  Emre Tuncer ,  Eric McCaughrin ,  Feroze Peshotan Taraporevala ,  Gary K. Yeap ,  James S. Koford ,  Joseph T. Rahmeh ,  Lilly Shieh ,  Salil R. Raje ,  Sam Jung Kim ,  Satamurthy Pullela ,  Yau-Tsun Steven Li ,  Tong Gao

发明人： Lawrence Pileggi ,  Majid Sarrafzadeh ,  Sharad Malik ,  Abhijeet Chakraborty ,  Archie Li ,  Robert Eugene Shortt ,  Christopher Dunn ,  David Gluss ,  Dennis Yamamoto ,  Dinesh Gaitonde ,  Douglas B. Boyle ,  Emre Tuncer ,  Eric McCaughrin ,  Feroze Peshotan Taraporevala ,  Gary K. Yeap ,  James S. Koford ,  Joseph T. Rahmeh ,  Lilly Shieh ,  Salil R. Raje ,  Sam Jung Kim ,  Satamurthy Pullela ,  Yau-Tsun Steven Li ,  Tong Gao

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F2217/78

摘要： A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

摘要翻译： 提供了使用逻辑和物理信息进行设计优化的方法。 在一个实施例中，使用逻辑和物理信息的设计优化的方法包括接收集成电路或集成电路的一部分的行为描述，根据第一成本函数优化电路元件的布局，以及优化逻辑 根据第二成本函数的电路元件，其中同时执行电路元件的优化布置和电路元件的优化逻辑。 该方法可以进一步包括根据第三成本函数优化路由，其中​​同时执行优化路由，电路元件的优化布局和电路元件的优化逻辑。

公开(公告)号：US08677302B2

公开(公告)日：2014-03-18

申请号：US12695452

申请日：2010-01-28

申请人： Tong Gao

发明人： Tong Gao

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a set of partitions for a circuit design, wherein each partition has zero or more overlapping partitions along four directions, e.g., up, down, left, and right. Next, the system can perform, in parallel, detailed routing on non-overlapping partitions in the set of partitions, wherein detailed routing is performed on a partition after detailed routing is completed on adjacent or overlapping partitions that located along two perpendicular directions. In some embodiments, each detailed routing thread that is executing in parallel performs detailed routing on a different net.

摘要翻译： 一些实施例提供用于并行地在电路设计中布线网络的技术和系统。 在操作期间，系统可以接收用于电路设计的一组分区，其中每个分区在四个方向上具有零个或多个重叠的分区，例如上，下，左，右。 接下来，系统可以并行地执行在该组分区中的非重叠分区上的详细路由，其中​​在沿着两个垂直方向定位的相邻或重叠分区上完成详细路由之后在分区上执行详细路由。 在一些实施例中，并行执行的每个详细路由线程在不同的网上执行详细路由。

公开(公告)号：US08527930B2

公开(公告)日：2013-09-03

申请号：US12695513

申请日：2010-01-28

申请人： Linni Wen ,  Tong Gao

发明人： Linni Wen ,  Tong Gao

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Some embodiments of the present invention provide systems for generating and using a route fix guidance for fixing design rule violations. A route fix guidance includes information that enables a router to locally modify a routing solution to fix one or more design rule violations. A route fix guidance can include a set of two or more metal avoidance areas, wherein avoiding any one of the set of two or more metal avoidance areas during routing fixes the design rule violation. Additionally, a route fix guidance can specify a set of rectangles to remove from a routing solution, and a set of rectangles to insert into or add to a routing solution. Further, the route fix guidance can include information for moving one or more vias to new locations in the routing solution. The route fix guidance can specify a sequence in which the local modifications are to be made.

摘要翻译： 本发明的一些实施例提供用于生成和使用用于固定设计规则违规的路线固定引导的系统。 路由修复指南包括使路由器能够本地修改路由解决方案以修复一个或多个设计规则违规的信息。 路线固定引导件可以包括一组两个或多个金属回避区域，其中在路由期间避免该组两个或多个金属回避区域中的任何一个固定了设计规则违规。 另外，路由修复引导可以指定要从路由解决方案中移除的一组矩形以及一组插入或添加到路由解决方案中的矩形。 此外，路线修复引导可以包括用于将一个或多个通孔移动到路由解决方案中的新位置的信息。 路线修复指导可以指定要进行局部修改的顺序。

公开(公告)号：US20110055791A1

公开(公告)日：2011-03-03

申请号：US12608434

申请日：2009-10-29

申请人： Tong Gao

发明人： Tong Gao

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/72

摘要： One embodiment of the present invention provides a system that concurrently optimizes multiple routing objectives during routing of an integrated circuit (IC) chip design. During operation, the system starts by receiving a routing solution for the IC chip design and a set of routing objectives. The system then partitions the IC chip design into a set of partitions. Next, for each partition in the set of partitions, the system optimizes the routing solution by, iteratively: (1) analyzing the routing solution to determine weights for the set of routing objectives; (2) constructing a cost function based on the weights for the set of routing objectives; and (3) modifying the routing solution within the partition to attempt to optimize the cost function.

摘要翻译： 本发明的一个实施例提供了一种在集成电路（IC）芯片设计的路由期间同时优化多个路由目标的系统。 在运行期间，系统通过接收IC芯片设计的路由解决方案和一组路由目标来启动。 然后，系统将IC芯片设计分成一组分区。 接下来，对于分组集合中的每个分区，系统通过迭代地优化路由解决方案：（1）分析路由解决方案以确定路由目标集合的权重; （2）基于路由目标集合的权重构建成本函数; 和（3）修改分区内的路由解决方案，尝试优化成本函数。

公开(公告)号：US20090011672A1

公开(公告)日：2009-01-08

申请号：US11816966

申请日：2006-03-03

申请人： Tong Gao ,  Alberto Lora Lamia

发明人： Tong Gao ,  Alberto Lora Lamia

IPC分类号： D06C7/02 ,  D04B1/18 ,  D03D15/08

CPC分类号： D03D15/08 ,  D04B1/18 ,  D06C7/02 ,  D10B2211/02 ,  Y10T442/3008

摘要： The present disclosure is directed to washable wool stretch or elastic textile articles which are dimensionally stable. Preferably, the articles are characterized in that they have not been subjected to temperatures greater than 1600 C. The disclosure is also directed to a method to make dimensionally stable wool stretch articles characterized by the absence of a traditional heat-setting step.

摘要翻译： 本公开涉及尺寸稳定的可洗羊毛拉伸或弹性织物制品。 优选地，制品的特征在于它们没有经受大于1600℃的温度。本发明还涉及一种制造尺寸稳定的羊毛拉伸制品的方法，其特征在于不存在传统的热定型步骤。

公开(公告)号：US06651232B1

公开(公告)日：2003-11-18

申请号：US09186430

申请日：1998-11-05

申请人： Lawrence Pileggi ,  Christopher Dunn ,  Satyamurthy Pullela ,  Majid Sarrafzadeh ,  Tong Gao ,  Salil Raje

发明人： Lawrence Pileggi ,  Christopher Dunn ,  Satyamurthy Pullela ,  Majid Sarrafzadeh ,  Tong Gao ,  Salil Raje

IPC分类号： G06F1750

CPC分类号： G06F1/10 ,  G06F17/5077

摘要： Progressively optimized clock tree/mesh construction is performed concurrently with placement of all remaining objects. Clock tree/mesh is specified loosely for initial placement, then followed by progressive detailed placement. In particular, preferred approach provides automated and reliable solution to clock tree/mesh construction, occuring concurrently with placement process so that clock tree wiring and buffering considers and influences placement and wiring of all other objects, such as logic gates, memory elements, macrocells, etc. Hence, in this concurrent manner, clock tree/mesh pre-wiring and pre-buffering may be based on construction of approximate clock tree using partitioning information only, i.e., prior to object placement. Further, present approach provides modified DME-based clock tree topology construction without meandering, and recursive algorithm for buffered clock tree construction.

摘要翻译： 逐渐优化的时钟树/网格构建与所有剩余对象的放置同时执行。 时钟树/网格被松散地指定用于初始放置，然后是渐进的详细放置。 特别地，优选的方法为时钟树/网格构造提供了自动化和可靠的解决方案，与布置过程同时发生，使得时钟树布线和缓冲考虑并影响所有其他对象（诸如逻辑门，存储器元件，宏单元）的布局和布线， 因此，以这种并发方式，时钟树/网格预接线和预缓冲可以基于仅使用分区信息（即，在对象放置之前）构建近似时钟树。 此外，目前的方法提供了基于改进的基于DME的时钟树拓扑构造而不进行曲折，并且缓冲时钟树构建的递归算法。