公开(公告)号：US20240363755A1

公开(公告)日：2024-10-31

申请号：US18531497

申请日：2023-12-06

申请人： Adeia Semiconductor Solutions LLC

发明人： Huiming Bu ,  Kangguo Cheng ,  Dechao Guo ,  Sivananda K. Kanakasabapathy ,  Peng Xu

IPC分类号： H01L29/78 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

摘要： A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

公开(公告)号：US11894462B2

公开(公告)日：2024-02-06

申请号：US17511134

申请日：2021-10-26

申请人： Adeia Semiconductor Solutions LLC

发明人： Huiming Bu ,  Kangguo Cheng ,  Dechao Guo ,  Sivananda K. Kanakasabapathy ,  Peng Xu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/324

CPC分类号： H01L29/785 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

摘要： A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.