公开(公告)号：US20060028241A1

公开(公告)日：2006-02-09

申请号：US11186923

申请日：2005-07-22

申请人： Adrian Apostol ,  Petrica Avram ,  Romeo Iacobut ,  Adam Levinthal ,  Zvi Or-Bach ,  Ze'ev Wurman ,  Richard Zeman ,  Alon Kapel ,  George Grigore

发明人： Adrian Apostol ,  Petrica Avram ,  Romeo Iacobut ,  Adam Levinthal ,  Zvi Or-Bach ,  Ze'ev Wurman ,  Richard Zeman ,  Alon Kapel ,  George Grigore

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

公开(公告)号：US07157937B2

公开(公告)日：2007-01-02

申请号：US11186923

申请日：2005-07-22

申请人： Adrian Apostol ,  Petrica Avram ,  Romeo Iacobut ,  Adam Levinthal ,  Zvi Or-Bach ,  Ze′ev Wurman ,  Richard Zeman ,  Alon Kapel ,  George C. Grigore

发明人： Adrian Apostol ,  Petrica Avram ,  Romeo Iacobut ,  Adam Levinthal ,  Zvi Or-Bach ,  Ze′ev Wurman ,  Richard Zeman ,  Alon Kapel ,  George C. Grigore

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

摘要翻译： 可配置的逻辑阵列可以包括：多个逻辑单元，其包含查找表; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 以及具有可自定义I / O的微处理器，用于配置和测试阵列，其中的定制都在单个通孔层上完成。

公开(公告)号：US07550996B2

公开(公告)日：2009-06-23

申请号：US11366528

申请日：2006-03-03

申请人： Zvi Or-Bach ,  Petrica Avram ,  Romeo Iacobut ,  Adrian Apostol ,  Ze'ev Wurman ,  Adam Levinthal ,  Richard Zeman

发明人： Zvi Or-Bach ,  Petrica Avram ,  Romeo Iacobut ,  Adrian Apostol ,  Ze'ev Wurman ,  Adam Levinthal ,  Richard Zeman

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.

摘要翻译： 可配置的逻辑阵列可以包括：多个逻辑单元，其包含查找表; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 和/或具有可定制I / O的微处理器，可用于配置和测试阵列，其中定制全部在单个通孔层上完成。

公开(公告)号：US20060164121A1

公开(公告)日：2006-07-27

申请号：US11366528

申请日：2006-03-03

申请人： Zvi Or-Bach ,  Petrica Avram ,  Romeo Iacobut ,  Adrian Apostol ,  Ze'ev Wurman ,  Adam Levinthal ,  Richard Zeman

发明人： Zvi Or-Bach ,  Petrica Avram ,  Romeo Iacobut ,  Adrian Apostol ,  Ze'ev Wurman ,  Adam Levinthal ,  Richard Zeman

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.

公开(公告)号：US07098691B2

公开(公告)日：2006-08-29

申请号：US10899020

申请日：2004-07-27

申请人： Zvi Or-Bach ,  Petrica Avram ,  Romeo Iacobut ,  Adrian Apostol ,  Ze'ev Wurman ,  Adam Leventhal ,  Richard Zeman

发明人： Zvi Or-Bach ,  Petrica Avram ,  Romeo Iacobut ,  Adrian Apostol ,  Ze'ev Wurman ,  Adam Leventhal ,  Richard Zeman

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

公开(公告)号：US20060022705A1

公开(公告)日：2006-02-02

申请号：US10899020

申请日：2004-07-27

申请人： Zvi Or-Bach ,  Petrica Avram ,  Romeo Iacobut ,  Adrian Apostol ,  Ze'ev Wurman ,  Adam Leventhal ,  Richard Zeman

发明人： Zvi Or-Bach ,  Petrica Avram ,  Romeo Iacobut ,  Adrian Apostol ,  Ze'ev Wurman ,  Adam Leventhal ,  Richard Zeman

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  G01R31/3172 ,  G01R31/318516 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

摘要： A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.