公开(公告)号：US12222797B2

公开(公告)日：2025-02-11

申请号：US18084499

申请日：2022-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： James Mossman ,  Robert Cohen ,  Sudherssen Kalaiselvan ,  Tzu-Wei Lin

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F1/3296

Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240201777A1

公开(公告)日：2024-06-20

申请号：US18084499

申请日：2022-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： James Mossman ,  Robert Cohen ,  Sudherssen Kalaiselvan ,  Tzu-Wei Lin

IPC: G06F1/3296 ,  G06F1/3287

CPC classification number: G06F1/3296 ,  G06F1/3287

Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11907126B2

公开(公告)日：2024-02-20

申请号：US17116950

申请日：2020-12-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. Cohen ,  Tzu-Wei Lin ,  Anthony J. Bybell ,  Sudherssen Kalaiselvan ,  James Mossman

IPC: G06F9/38 ,  G06F12/0855

CPC classification number: G06F12/0855 ,  G06F9/3808 ,  G06F9/3814 ,  G06F2212/60

Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.