公开(公告)号：US20180060257A1

公开(公告)日：2018-03-01

申请号：US15663403

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron NYGREN ,  Michael IGNATOWSKI ,  David A. ROBERTS

IPC: G06F13/16 ,  G06F11/10

CPC classification number: G06F13/1673 ,  G06F11/1004 ,  G06F13/1689

Abstract: A memory module includes a memory, a cache to cache copies of information stored in the memory, and a controller. The controller is configured to access first data from the memory or the cache in response to receiving a read request from a processor. The controller is also configured to transmit a first signal a first nondeterministic time interval after receiving the read request. The first signal indicates that the first data is available. The controller is further configured to transmit a second signal a first deterministic time interval after receiving a first transmit request from the processor in response to the first signal. The second signal includes the first data. The memory module also includes a buffer to store a write request until completion and a counter that is incremented in response to receiving the write request and decremented in response to completing the write request.