公开(公告)号：US20180060257A1

公开(公告)日：2018-03-01

申请号：US15663403

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron NYGREN ,  Michael IGNATOWSKI ,  David A. ROBERTS

IPC: G06F13/16 ,  G06F11/10

CPC classification number: G06F13/1673 ,  G06F11/1004 ,  G06F13/1689

Abstract: A memory module includes a memory, a cache to cache copies of information stored in the memory, and a controller. The controller is configured to access first data from the memory or the cache in response to receiving a read request from a processor. The controller is also configured to transmit a first signal a first nondeterministic time interval after receiving the read request. The first signal indicates that the first data is available. The controller is further configured to transmit a second signal a first deterministic time interval after receiving a first transmit request from the processor in response to the first signal. The second signal includes the first data. The memory module also includes a buffer to store a write request until completion and a counter that is incremented in response to receiving the write request and decremented in response to completing the write request.

公开(公告)号：US20190095330A1

公开(公告)日：2019-03-28

申请号：US15718564

申请日：2017-09-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A. ROBERTS ,  Elliot H. MEDNICK

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/084 ,  G06F12/0804

CPC classification number: G06F12/0831 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/507 ,  G06F2212/60 ,  G06F2212/621

Abstract: A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.

公开(公告)号：US20190371400A1

公开(公告)日：2019-12-05

申请号：US16533278

申请日：2019-08-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Amin FARMAHINI FARAHANI ,  David A. ROBERTS

IPC: G11C14/00 ,  H01L27/108 ,  G11C7/10

Abstract: A high-performance on-module caching architecture for hybrid memory modules is provided. A hybrid memory module includes a cache controller, a first volatile memory coupled to the cache controller, a first multiplexing data buffer coupled to the first volatile memory and the cache controller, and a first non-volatile memory coupled to the first multiplexing data buffer and the cache controller, wherein the first multiplexing data buffer multiplexes data between the first volatile memory and the first non-volatile memory and wherein the cache controller enables a tag checking operation to occur in parallel with a data movement operation. The hybrid memory module includes a volatile memory tag unit coupled to the cache controller, wherein the volatile memory tag unit includes a line connection that allows the cache controller to store a plurality of tags in the volatile memory tag unit and retrieve the plurality of tags from the volatile memory tag unit.

公开(公告)号：US20190189210A1

公开(公告)日：2019-06-20

申请号：US15841997

申请日：2017-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Amin FARMAHINI FARAHANI ,  David A. ROBERTS

IPC: G11C14/00 ,  G11C7/10 ,  H01L27/108

CPC classification number: G11C14/0018 ,  G11C5/04 ,  G11C7/1084 ,  G11C11/005 ,  G11C2207/2245 ,  H01L27/108

Abstract: A high-performance on-module caching architecture for hybrid memory modules is provided. A hybrid memory module includes a cache controller, a first volatile memory coupled to the cache controller, a first multiplexing data buffer coupled to the first volatile memory and the cache controller, and a first non-volatile memory coupled to the first multiplexing data buffer and the cache controller, wherein the first multiplexing data buffer multiplexes data between the first volatile memory and the first non-volatile memory and wherein the cache controller enables a tag checking operation to occur in parallel with a data movement operation. The hybrid memory module includes a volatile memory tag unit coupled to the cache controller, wherein the volatile memory tag unit includes a line connection that allows the cache controller to store a plurality of tags in the volatile memory tag unit and retrieve the plurality of tags from the volatile memory tag unit.

公开(公告)号：US20150095605A1

公开(公告)日：2015-04-02

申请号：US14044454

申请日：2013-10-02

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. ROBERTS ,  Michael Ignatowski

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/068 ,  G06F13/1642 ,  G06F13/1668 ,  Y02D10/14

Abstract: A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.

Abstract translation: 提供了一种用于访问异构存储器系统的系统，方法和计算机可读存储设备。 存储器控制器基于与命令相关联的访问优先级来调度对一组存储器区域中的存储器区域的访问，并且其中该组存储器区域具有相应的访问延迟。 存储器控制器还使用至少两个队列和访问优先级来延迟对该组存储器区域的访问。