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    Branch target buffer with early return prediction
    2.
    发明授权
    Branch target buffer with early return prediction 有权

    公开(公告)号：US11055098B2

    公开(公告)日：2021-07-06

    申请号：US16043293

    申请日：2018-07-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Aparna Thyagarajan ,  Marius Evers ,  Arunachalam Annamalai

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A processor includes a branch target buffer (BTB) having a plurality of entries whereby each entry corresponds to an associated instruction pointer value that is predicted to be a branch instruction. Each BTB entry stores a predicted branch target address for the branch instruction, and further stores information indicating whether the next branch in the block of instructions associated with the predicted branch target address is predicted to be a return instruction. In response to the BTB indicating that the next branch is predicted to be a return instruction, the processor initiates an access to a return stack that stores the return address for the predicted return instruction. By initiating access to the return stack responsive to the return prediction stored at the BTB, the processor reduces the delay in identifying the return address, thereby improving processing efficiency.

    Using loop exit prediction to accelerate or suppress loop mode of a processor
    3.
    发明授权
    Using loop exit prediction to accelerate or suppress loop mode of a processor 有权

    公开(公告)号：US10915322B2

    公开(公告)日：2021-02-09

    申请号：US16134440

    申请日：2018-09-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Arunachalam Annamalai ,  Marius Evers ,  Aparna Thyagarajan ,  Anthony Jarvis

    IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3296

    Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

    Selectively performing ahead branch prediction based on types of branch instructions
    4.
    发明授权
    Selectively performing ahead branch prediction based on types of branch instructions 有权

    公开(公告)号：US10732979B2

    公开(公告)日：2020-08-04

    申请号：US16011010

    申请日：2018-06-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Marius Evers ,  Aparna Thyagarajan ,  Ashok T. Venkatachar

    IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/355 ,  G06F9/35

    Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.

    Selectively performing ahead branch prediction based on types of branch instructions
    6.
    发明授权
    Selectively performing ahead branch prediction based on types of branch instructions 有权

    公开(公告)号：US11416256B2

    公开(公告)日：2022-08-16

    申请号：US16945275

    申请日：2020-07-31

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Marius Evers ,  Aparna Thyagarajan ,  Ashok T. Venkatachar

    IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/355 ,  G06F9/35

    Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.

    Using loop exit prediction to accelerate or suppress loop mode of a processor
    7.
    发明授权
    Using loop exit prediction to accelerate or suppress loop mode of a processor 有权

    公开(公告)号：US11256505B2

    公开(公告)日：2022-02-22

    申请号：US17169053

    申请日：2021-02-05

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Arunachalam Annamalai ,  Marius Evers ,  Aparna Thyagarajan ,  Anthony Jarvis

    IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3296

    Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

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