公开(公告)号：US10089155B2

公开(公告)日：2018-10-02

申请号：US14862038

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Deepak Majeti ,  Mauricio Breternitz

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/32 ,  G06F1/20

Abstract: First and second processor cores are configured to concurrently execute tasks. A scheduler is configured to schedule tasks for execution by the first and second processor cores. The first processor core is configured to selectively steal a task that was previously scheduled for execution by the second processor core based on additional power consumption incurred by migrating the task from the second processor core to the first processor core.

公开(公告)号：US20170083382A1

公开(公告)日：2017-03-23

申请号：US14862038

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Deepak Majeti ,  Mauricio Breternitz

IPC: G06F9/50 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F9/5094 ,  G06F1/206 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/4856 ,  G06F9/4893 ,  Y02D10/152 ,  Y02D10/16 ,  Y02D10/24

Abstract: First and second processor cores are configured to concurrently execute tasks. A scheduler is configured to schedule tasks for execution by the first and second processor cores. The first processor core is configured to selectively steal a task that was previously scheduled for execution by the second processor core based on additional power consumption incurred by migrating the task from the second processor core to the first processor core.