公开(公告)号：US20240004823A1

公开(公告)日：2024-01-04

申请号：US17855106

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Brian Mitchell ,  George D. Azevedo

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/4282 ,  G06F2213/0028 ,  G06F2213/0026

Abstract: An apparatus and method for efficiently supporting multiple peripheral communication protocols in a computing system. A computing system includes multiple servers with one or more of the servers using multiple connectors for connecting to multiple peripheral devices such as data storage devices. At least one of the connectors is able to support multiple communication protocols, rather than a single communication protocol. A processor of the server determines a peripheral device has been attached to a connector that supports multiple communication protocols, and the processor determines whether one of the multiple communication protocols supported by the particular connector matches the attached peripheral device's communication protocol. If so, the processor configures the connector with the matching communication protocol. Otherwise, the processor generates an indication that specifies that there is no match.

公开(公告)号：US20240004822A1

公开(公告)日：2024-01-04

申请号：US17854490

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： George D. Azevedo ,  Peter Malcolm Barnes ,  Michael J. Tresidder

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/409 ,  G06F13/4221 ,  G06F15/7807

Abstract: Systems, apparatuses, and methods for automatic firmware provision of high speed serializer/deserializer (SERDES) links are disclosed. A system on chip (SoC) includes one or more microcontrollers, a programmable interconnect, a plurality of physical layer engines, and a plurality of SERDES lanes. The programmable interconnect and the plurality of SERDES lanes are able to support communication protocols for interfaces such as PCIE, SATA, Ethernet, and others. On bootup, the SoC receives a custom specification of how the plurality of SERDES lanes are to be configured. The one or more microcontrollers generate a mapping for the programmable interconnect based on the specification. The mapping is used to configure the programmable interconnect to match the specification. The result is the programmable interconnect connecting the plurality of SERDES lanes to the appropriate physical layer circuits to implement the desired configuration.