公开(公告)号：US09710589B2

公开(公告)日：2017-07-18

申请号：US14748795

申请日：2015-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Kalpeshkumar Girishchandra Dave ,  Naveen Chandra Srivastava ,  Pankaj Kumar ,  Janardhan Achanta ,  Shreekanth Karandoor Sampigethaya

IPC: G06F17/50 ,  H01L21/28 ,  H01L21/8234 ,  G03F7/00

CPC classification number: G06F17/5072 ,  G03F7/0002 ,  G06F17/5081 ,  H01L21/28123 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475

Abstract: Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.

公开(公告)号：US20160378899A1

公开(公告)日：2016-12-29

申请号：US14748795

申请日：2015-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Kalpeshkumar Girishchandra Dave ,  Naveen Chandra Srivastava ,  Pankaj Kumar ,  Janardhan Achanta ,  Shreekanth Karandoor Sampigethaya

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F7/0002 ,  G06F17/5081 ,  H01L21/28123 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475

Abstract: Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.

Abstract translation: 减小半导体结构面积的系统，装置和方法。 对于用于分离半导体材料层的第一和第二区域的间隙宽度，可以检测到间隔冲突。 响应于检测到违规，将第一和第二区域合并成组合区域，然后在组合区域上形成切割掩模层。 接下来，通过切割掩模层进行蚀刻处理以去除组合区域内的暴露的第三区域，其中暴露的第三区域插入在组合区域的第一和第二区域部分之间。