公开(公告)号：US09898568B2

公开(公告)日：2018-02-20

申请号：US14748075

申请日：2015-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Naveen Chandra Srivastava ,  Janardhan Achanta ,  Pankaj Kumar ,  Shreekanth Karandoor Sampigethaya

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/78

Abstract: Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.

公开(公告)号：US20160378898A1

公开(公告)日：2016-12-29

申请号：US14748075

申请日：2015-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Naveen Chandra Srivastava ,  Janardhan Achanta ,  Pankaj Kumar ,  Shreekanth Karandoor Sampigethaya

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/78

Abstract: Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.

Abstract translation: 描述了用于减小ROM位单元阵列的位线的负载的系统，装置和方法。 可以使用传统方法基于其编程值来分配ROM位单元阵列的网络之间的连接。 然后，可以对网络的分配执行多个优化，以减少阵列的位线的负载。 响应于检测到对应位线的连接数量大于给定列的连接数量，第一优化可以互换给定列的地线和位线之间的连接。 如果给定列的三个连续网络连接到位线，则第二个优化可以将网络连接到位线。

公开(公告)号：US09710589B2

公开(公告)日：2017-07-18

申请号：US14748795

申请日：2015-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Kalpeshkumar Girishchandra Dave ,  Naveen Chandra Srivastava ,  Pankaj Kumar ,  Janardhan Achanta ,  Shreekanth Karandoor Sampigethaya

IPC: G06F17/50 ,  H01L21/28 ,  H01L21/8234 ,  G03F7/00

CPC classification number: G06F17/5072 ,  G03F7/0002 ,  G06F17/5081 ,  H01L21/28123 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475

Abstract: Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.

公开(公告)号：US20160378899A1

公开(公告)日：2016-12-29

申请号：US14748795

申请日：2015-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Kalpeshkumar Girishchandra Dave ,  Naveen Chandra Srivastava ,  Pankaj Kumar ,  Janardhan Achanta ,  Shreekanth Karandoor Sampigethaya

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F7/0002 ,  G06F17/5081 ,  H01L21/28123 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475

Abstract: Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.

Abstract translation: 减小半导体结构面积的系统，装置和方法。 对于用于分离半导体材料层的第一和第二区域的间隙宽度，可以检测到间隔冲突。 响应于检测到违规，将第一和第二区域合并成组合区域，然后在组合区域上形成切割掩模层。 接下来，通过切割掩模层进行蚀刻处理以去除组合区域内的暴露的第三区域，其中暴露的第三区域插入在组合区域的第一和第二区域部分之间。