公开(公告)号：US20150317249A1

公开(公告)日：2015-11-05

申请号：US14682757

申请日：2015-04-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Jaewoong Chung ,  Shekhar Srikantaiah ,  Lisa Hsu

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0842 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/62

Abstract: For each access request received at a shared cache of the data processing device, a memory access pattern (MAP) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the MAP monitor develops a pattern of predicted memory accesses by executing threads. The pattern can be employed to assign resources at the shared cache, thereby managing memory more efficiently.

Abstract translation: 对于在数据处理设备的共享高速缓存处接收到的每个访问请求，如果请求的线程是唯一的线程，则存储器访问模式（MAP）监视器预测访问请求将访问哪个存储体和对应的行缓冲器 在数据处理装置执行。 通过针对多个访问请求记录对时间的预测访问，MAP监视器通过执行线程来开发预测的存储器访问的模式。 可以使用该模式来在共享高速缓存上分配资源，从而更有效地管理存储器。

公开(公告)号：US20140181460A1

公开(公告)日：2014-06-26

申请号：US13723379

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lisa Hsu ,  Nuwan Jayasena ,  Andrew Kegel ,  Bradford M. Beckmann

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1081 ,  G06F2212/302 ,  G06F2212/681 ,  G06F2212/684

Abstract: A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of a page table of a memory shared by the processors. The processing device is configured such that when an address translation is requested by a processor and is not found in the TLB associated with that processor, another TLB is probed for the requested address translation. The probe across to the other TLB may occur in advance of a walk of the page table for the requested address or alternatively a walk can be initiated concurrently with the probe. Where the probe successfully finds the requested address translation, the page table walk can be avoided or discontinued.

Abstract translation: 提供了一种数据处理设备，其采用与相应处理器相关联的多个翻译后备缓冲器（TLB），其配置为存储由处理器共享的存储器的页表的所选地址转换。 处理装置被配置为使得当处理器请求地址转换并且在与该处理器相关联的TLB中没有找到地址转换时，探测另一TLB用于请求的地址转换。 跨越其他TLB的探针可以在针对所请求的地址的页表的行进之前发生，或者可以与探针同时启动步行。 探头成功找到所请求的地址转换的地方，可以避免或停止页表的移动。

公开(公告)号：US09697125B2

公开(公告)日：2017-07-04

申请号：US14682757

申请日：2015-04-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Jaewoong Chung ,  Shekhar Srikantaiah ,  Lisa Hsu

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/126 ,  G06F12/123

CPC classification number: G06F12/084 ,  G06F12/0842 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/62

Abstract: For each access request received at a shared cache of the data processing device, a memory access pattern (MAP) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the MAP monitor develops a pattern of predicted memory accesses by executing threads. The pattern can be employed to assign resources at the shared cache, thereby managing memory more efficiently.

公开(公告)号：US08984255B2

公开(公告)日：2015-03-17

申请号：US13723379

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Lisa Hsu ,  Nuwan Jayasena ,  Andrew Kegel ,  Bradford M. Beckmann

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1081 ,  G06F2212/302 ,  G06F2212/681 ,  G06F2212/684

Abstract: A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of a page table of a memory shared by the processors. The processing device is configured such that when an address translation is requested by a processor and is not found in the TLB associated with that processor, another TLB is probed for the requested address translation. The probe across to the other TLB may occur in advance of a walk of the page table for the requested address or alternatively a walk can be initiated concurrently with the probe. Where the probe successfully finds the requested address translation, the page table walk can be avoided or discontinued.

Abstract translation: 提供了一种数据处理设备，其采用与相应处理器相关联的多个翻译后备缓冲器（TLB），其被配置为存储由处理器共享的存储器的页表的所选地址转换。 处理装置被配置为使得当处理器请求地址转换并且在与该处理器相关联的TLB中没有找到地址转换时，探测另一TLB用于请求的地址转换。 跨越其他TLB的探针可以在针对所请求的地址的页表的行进之前发生，或者可以与探针同时启动步行。 探头成功找到所请求的地址转换的地方，可以避免或停止页表的移动。