公开(公告)号：US12169896B2

公开(公告)日：2024-12-17

申请号：US17489105

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey ,  Michael J. Mantor ,  Christopher J. Brennan ,  Mark M. Leather ,  Ryan James Cash

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses, and methods for preemptively reserving buffer space for primitives and positions in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with any number of geometry engines coupled to corresponding shader engines. Each geometry engine launches shader wavefronts to execute on a corresponding shader engine. The geometry engine preemptively reserves buffer space for each wavefront prior to the wavefront being launched on the shader engine. When the shader engine executes a wavefront, the shader engine exports primitive and position data to the reserved buffer space. Multiple scan converters will consume the primitive and position data, with each scan converter consuming primitive and position data based on the screen coverage of the scan converter. After consuming the primitive and position data, the scan converters mark the buffer space as freed so that the geometry engine can then allocate the freed buffer space to subsequent shader wavefronts.

公开(公告)号：US20230095365A1

公开(公告)日：2023-03-30

申请号：US17489059

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey

IPC: G06F9/4401 ,  G06F9/30 ,  G06F9/54

Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.

公开(公告)号：US12062126B2

公开(公告)日：2024-08-13

申请号：US17489008

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: Systems, apparatuses, and methods for loading multiple primitives per thread in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with a geometry engine, shader processor input (SPI), and a plurality of compute units. The geometry engine generates primitives which are accumulated by the SPI into primitive groups. While accumulating primitives, the SPI tracks the number of vertices and primitives per group. The SPI determines wavefront boundaries based on mapping a single vertex to each thread of the wavefront while allowing more than one primitive per thread. The SPI launches wavefronts with one vertex per thread and potentially multiple primitives per thread. The compute units execute a vertex phase and a multi-cycle primitive phase for wavefronts with multiple primitives per thread.

公开(公告)号：US20240070961A1

公开(公告)日：2024-02-29

申请号：US18089456

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael John Livesley ,  Vishrut Vaibhav ,  Tad Robert Litwiller

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/52

Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler.

公开(公告)号：US11755336B2

公开(公告)日：2023-09-12

申请号：US17489059

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey

IPC: G06T1/60 ,  G06F9/4401 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06F9/4411 ,  G06F9/3009 ,  G06F9/544

Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.

公开(公告)号：US20240169641A1

公开(公告)日：2024-05-23

申请号：US18193988

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vishrut Vaibhav ,  Michael John Livesley ,  Tad Robert Litwiller

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/52

Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include providing indices and vertices to a culling shader; culling primitives and outputting primitives and indices that are not culled; and generating information for a fine binning pass based on the indices and primitives that are not culled.

公开(公告)号：US20230376318A1

公开(公告)日：2023-11-23

申请号：US18363333

申请日：2023-08-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey

IPC: G06F9/4401 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06F9/4411 ,  G06F9/3009 ,  G06F9/544

Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.

公开(公告)号：US20230097097A1

公开(公告)日：2023-03-30

申请号：US17489105

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey ,  Michael J. Mantor ,  Christopher J. Brennan ,  Mark M. Leather ,  Ryan James Cash

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses, and methods for preemptively reserving buffer space for primitives and positions in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with any number of geometry engines coupled to corresponding shader engines. Each geometry engine launches shader wavefronts to execute on a corresponding shader engine. The geometry engine preemptively reserves buffer space for each wavefront prior to the wavefront being launched on the shader engine. When the shader engine executes a wavefront, the shader engine exports primitive and position data to the reserved buffer space. Multiple scan converters will consume the primitive and position data, with each scan converter consuming primitive and position data based on the screen coverage of the scan converter. After consuming the primitive and position data, the scan converters mark the buffer space as freed so that the geometry engine can then allocate the freed buffer space to subsequent shader wavefronts.

公开(公告)号：US20230094115A1

公开(公告)日：2023-03-30

申请号：US17489008

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey

IPC: G06T15/00

Abstract: Systems, apparatuses, and methods for loading multiple primitives per thread in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with a geometry engine, shader processor input (SPI), and a plurality of compute units. The geometry engine generates primitives which are accumulated by the SPI into primitive groups. While accumulating primitives, the SPI tracks the number of vertices and primitives per group. The SPI determines wavefront boundaries based on mapping a single vertex to each thread of the wavefront while allowing more than one primitive per thread. The SPI launches wavefronts with one vertex per thread and potentially multiple primitives per thread. The compute units execute a vertex phase and a multi-cycle primitive phase for wavefronts with multiple primitives per thread.