公开(公告)号：US20220076739A1

公开(公告)日：2022-03-10

申请号：US17526429

申请日：2021-11-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Naveen Davanam ,  Oswin E. Housty

IPC: G11C11/406 ,  G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/3234

Abstract: A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.

公开(公告)号：US20210201986A1

公开(公告)日：2021-07-01

申请号：US16730086

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Naveen Davanam ,  Oswin E. Housty

IPC: G11C11/406 ,  G06F12/02 ,  G06F1/3234 ,  G06F13/16 ,  G06F13/40

Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.

公开(公告)号：US20240112747A1

公开(公告)日：2024-04-04

申请号：US17957808

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Tahsin Askar ,  Naveen Davanam ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G11C29/10

CPC classification number: G11C29/10

Abstract: A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.

公开(公告)号：US11682445B2

公开(公告)日：2023-06-20

申请号：US17526429

申请日：2021-11-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Naveen Davanam ,  Oswin E. Housty

IPC: G11C11/406 ,  G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/3234

CPC classification number: G11C11/40622 ,  G06F1/3275 ,  G06F12/0238 ,  G06F13/1689 ,  G06F13/4072 ,  G06F13/4086

Abstract: A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.

公开(公告)号：US11176986B2

公开(公告)日：2021-11-16

申请号：US16730086

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Naveen Davanam ,  Oswin E. Housty

IPC: G11C7/00 ,  G11C11/406 ,  G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/3234

Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.