中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.017 seconds)

    MEMORY CONTEXT RESTORE, REDUCTION OF BOOT TIME OF A SYSTEM ON A CHIP BY REDUCING DOUBLE DATA RATE MEMORY TRAINING
    2.
    发明申请
    MEMORY CONTEXT RESTORE, REDUCTION OF BOOT TIME OF A SYSTEM ON A CHIP BY REDUCING DOUBLE DATA RATE MEMORY TRAINING 有权

    公开(公告)号：US20210201986A1

    公开(公告)日：2021-07-01

    申请号：US16730086

    申请日：2019-12-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin M. Brandl ,  Naveen Davanam ,  Oswin E. Housty

    IPC: G11C11/406 ,  G06F12/02 ,  G06F1/3234 ,  G06F13/16 ,  G06F13/40

    Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.

    DISTRIBUTED MULTI-CORE MEMORY INITIALIZATION
    3.
    发明申请
    DISTRIBUTED MULTI-CORE MEMORY INITIALIZATION 有权
    分布式多核存储器初始化

    公开(公告)号：US20130042096A1

    公开(公告)日：2013-02-14

    申请号：US13648648

    申请日：2012-10-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Oswin E. Housty

    IPC: G06F9/46 ,  G06F9/00

    CPC classification number: G06F9/4405

    Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

    Abstract translation: 在具有多个处理节点的系统中，控制节点将任务划分为多个子任务，并将子任务分配给执行所分配的子任务的一个或多个附加处理节点，并将结果返回给 从而使得多个处理节点能够有效地并且快速执行所有分配的子任务的存储器初始化和测试。

    Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training
    5.
    发明授权
    Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training 有权

    公开(公告)号：US11176986B2

    公开(公告)日：2021-11-16

    申请号：US16730086

    申请日：2019-12-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin M. Brandl ,  Naveen Davanam ,  Oswin E. Housty

    IPC: G11C7/00 ,  G11C11/406 ,  G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/3234

    Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.

    DDR 2D Vref training
    6.
    发明授权
    DDR 2D Vref training 有权
    DDR 2D Vref培训

    公开(公告)号：US09214199B2

    公开(公告)日：2015-12-15

    申请号：US14497977

    申请日：2014-09-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin M. Brandl ,  Oswin E. Housty ,  Gerald Talbot

    IPC: G06F12/00 ,  G11C7/00 ,  G11C29/02 ,  G06F3/06 ,  G06F13/16 ,  G06F12/16 ,  G11C11/40

    CPC classification number: G11C7/00 ,  G06F3/0614 ,  G06F3/0653 ,  G06F12/16 ,  G06F13/1689 ,  G11C11/40 ,  G11C29/021 ,  G11C29/028

    Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

    Abstract translation: 提供了一种用于响应于通过处理装置执行电压域中的双数据速率（DDR）存储器参考电压训练的指令执行存储器操作的方法，并且基于存储器确定DDR存储器参考电压和DDR存储器延迟时间 操作。 还提供计算机可读存储介质。 提供了一种电路，其包括耦合到存储器和处理设备的通信接口部分。 电路还包括耦合到具有硬件状态机或算法的通信接口部分的电路部分。 状态机或算法向处理设备提供指令以执行电压域中的双数据速率（DDR）参考电压训练。

    DDR 2D VREF TRAINING
    8.
    发明申请
    DDR 2D VREF TRAINING 审中-公开
    DDR 2D VREF培训

    公开(公告)号：US20150078104A1

    公开(公告)日：2015-03-19

    申请号：US14497977

    申请日：2014-09-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin M. Brandl ,  Oswin E. Housty ,  Gerald Talbot

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G06F3/0614 ,  G06F3/0653 ,  G06F12/16 ,  G06F13/1689 ,  G11C11/40 ,  G11C29/021 ,  G11C29/028

    Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

    Abstract translation: 提供了一种用于响应于通过处理装置执行电压域中的双数据速率（DDR）存储器参考电压训练的指令执行存储器操作的方法，并且基于存储器确定DDR存储器参考电压和DDR存储器延迟时间 操作。 还提供计算机可读存储介质。 提供了一种电路，其包括耦合到存储器和处理设备的通信接口部分。 电路还包括耦合到具有硬件状态机或算法的通信接口部分的电路部分。 状态机或算法向处理设备提供指令以执行电压域中的双数据速率（DDR）参考电压训练。

    Distributed multi-core memory initialization
    9.
    发明授权
    Distributed multi-core memory initialization 有权
    分布式多核内存初始化

    公开(公告)号：US08566570B2

    公开(公告)日：2013-10-22

    申请号：US13648648

    申请日：2012-10-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Oswin E. Housty

    IPC: G06F9/00 ,  G06F15/16 ,  G06F15/167 ,  G06F12/00 ,  G06F15/00 ,  G06F9/46 ,  G11C29/00

    CPC classification number: G06F9/4405

    Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

    Abstract translation: 在具有多个处理节点的系统中，控制节点将任务划分为多个子任务，并将子任务分配给执行所分配的子任务的一个或多个附加处理节点，并将结果返回给 从而使得多个处理节点能够有效地并且快速执行所有分配的子任务的存储器初始化和测试。

Patent Agency Ranking