公开(公告)号：US12039337B2

公开(公告)日：2024-07-16

申请号：US17032494

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. Cohen ,  Tzu-Wei Lin ,  Anthony J. Bybell ,  Bill Kai Chiu Kwan ,  Frank C. Galloway

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3804 ,  G06F9/30058 ,  G06F9/3822 ,  G06F9/3867

Abstract: A processor employs a plurality of fetch and decode pipelines by dividing an instruction stream into instruction blocks with identified boundaries. The processor includes a branch predictor that generates branch predictions. Each branch prediction corresponds to a branch instruction and includes a prediction that the corresponding branch is to be taken or not taken. In addition, each branch prediction identifies both an end of the current branch prediction window and the start of another branch prediction window. Using these known boundaries, the processor provides different sequential fetch streams to different ones of the plurality of fetch and decode states, which concurrently process the instructions of the different fetch streams, thereby improving overall instruction throughput at the processor.

公开(公告)号：US11907126B2

公开(公告)日：2024-02-20

申请号：US17116950

申请日：2020-12-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. Cohen ,  Tzu-Wei Lin ,  Anthony J. Bybell ,  Sudherssen Kalaiselvan ,  James Mossman

IPC: G06F9/38 ,  G06F12/0855

CPC classification number: G06F12/0855 ,  G06F9/3808 ,  G06F9/3814 ,  G06F2212/60

Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.

公开(公告)号：US20210406024A1

公开(公告)日：2021-12-30

申请号：US16913520

申请日：2020-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashok Tirupathy Venkatachar ,  Steven R. Havlir ,  Robert B. Cohen

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/1027

Abstract: Techniques for performing instruction fetch operations are provided. The techniques include determining instruction addresses for a primary branch prediction path; requesting that a level 0 translation lookaside buffer (“TLB”) caches address translations for the primary branch prediction path; determining either or both of alternate control flow path instruction addresses and lookahead control flow path instruction addresses; and requesting that either the level 0 TLB or an alternative level TLB caches address translations for either or both of the alternate control flow path instruction addresses and the lookahead control flow path instruction addresses.

公开(公告)号：US20140244932A1

公开(公告)日：2014-08-28

申请号：US13779573

申请日：2013-02-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Akarsh D. Hebbar ,  James D. Dundas ,  Robert B. Cohen

IPC: G06F12/08

CPC classification number: G06F12/0875

Abstract: The present invention provides a method and apparatus for caching pre-decode information. Some embodiments of the apparatus include a first pre-decode array configured to store pre-decode information for an instruction cache line that is resident in a first cache in response to the instruction cache line being evicted from one or more second cache(s). Some embodiments of the apparatus also include a second array configured to store a plurality of bits associated with the first cache. Subsets of the bits are configured to store pointers to the pre-decode information associated with the instruction cache line.

Abstract translation: 本发明提供了一种用于缓存预解码信息的方法和装置。 该装置的一些实施例包括第一预解码阵列，其被配置为存储响应于从一个或多个第二高速缓存逐出的指令高速缓存行驻留在第一高速缓存中的指令高速缓存线的预解码信息。 该装置的一些实施例还包括被配置为存储与第一高速缓存相关联的多个位的第二阵列。 位的子集被配置为存储与指令高速缓存行相关联的预解码信息的指针。

公开(公告)号：US11579884B2

公开(公告)日：2023-02-14

申请号：US16913520

申请日：2020-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashok Tirupathy Venkatachar ,  Steven R. Havlir ,  Robert B. Cohen

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/1027

Abstract: Techniques for performing instruction fetch operations are provided. The techniques include determining instruction addresses for a primary branch prediction path; requesting that a level 0 translation lookaside buffer (“TLB”) caches address translations for the primary branch prediction path; determining either or both of alternate control flow path instruction addresses and lookahead control flow path instruction addresses; and requesting that either the level 0 TLB or an alternative level TLB caches address translations for either or both of the alternate control flow path instruction addresses and the lookahead control flow path instruction addresses.