公开(公告)号：US20220237164A1

公开(公告)日：2022-07-28

申请号：US17721748

申请日：2022-04-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven R. Havlir ,  Patrick J. Shyvers

IPC: G06F16/22

Abstract: Described herein is a system and method for multiplexer tree (muxtree) indexing. Muxtree indexing performs hashing and row reduction in parallel by use of at least one bit in a lookup address at least once in a particular path of the muxtree. The muxtree indexing generates a different final index as compared to conventional hashed indexing but still results in a fair hash, where all table entries get used with equal distribution with uniformly random selects.

公开(公告)号：US20210406024A1

公开(公告)日：2021-12-30

申请号：US16913520

申请日：2020-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashok Tirupathy Venkatachar ,  Steven R. Havlir ,  Robert B. Cohen

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/1027

Abstract: Techniques for performing instruction fetch operations are provided. The techniques include determining instruction addresses for a primary branch prediction path; requesting that a level 0 translation lookaside buffer (“TLB”) caches address translations for the primary branch prediction path; determining either or both of alternate control flow path instruction addresses and lookahead control flow path instruction addresses; and requesting that either the level 0 TLB or an alternative level TLB caches address translations for either or both of the alternate control flow path instruction addresses and the lookahead control flow path instruction addresses.

公开(公告)号：US11782897B2

公开(公告)日：2023-10-10

申请号：US17721748

申请日：2022-04-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven R. Havlir ,  Patrick J. Shyvers

IPC: G06F16/22 ,  G06F9/38

CPC classification number: G06F16/2264 ,  G06F16/2246 ,  G06F16/2255 ,  G06F9/3844

Abstract: Described herein is a system and method for multiplexer tree (muxtree) indexing. Muxtree indexing performs hashing and row reduction in parallel by use of at least one bit in a lookup address at least once in a particular path of the muxtree. The muxtree indexing generates a different final index as compared to conventional hashed indexing but still results in a fair hash, where all table entries get used with equal distribution with uniformly random selects.

公开(公告)号：US20180060073A1

公开(公告)日：2018-03-01

申请号：US15252164

申请日：2016-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven R. Havlir

IPC: G06F9/38 ,  G06F12/0875 ,  G06F9/30

Abstract: Techniques for improving branch target buffer (“BTB”) operation. A compressed BTB is included within a branch prediction unit along with an uncompressed BTB. To support prediction of up to two branch instructions per cycle, the uncompressed BTB includes entries that each store data for up to two branch predictions. The compressed BTB includes entries that store data for only a single branch instruction for situations where storing that single branch instruction in the uncompressed BTB would waste space in that buffer. Space would be wasted in the uncompressed BTB due to the fact that, in order to support two branch lookups per cycle, prediction data for two branches must have certain features in common (such as cache line address) in order to be stored together in a single entry.

公开(公告)号：US12153927B2

公开(公告)日：2024-11-26

申请号：US16889010

申请日：2020-06-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas Clouqueur ,  Marius Evers ,  Aparna Mandke ,  Steven R. Havlir ,  Robert Cohen ,  Anthony Jarvis

IPC: G06F9/38 ,  G06F9/48

Abstract: Merging branch target buffer entries includes maintaining, in a branch target buffer, an entry corresponding to first branch instruction, where the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction; and accessing, based on the first branch instruction, the entry.

公开(公告)号：US10698691B2

公开(公告)日：2020-06-30

申请号：US15252168

申请日：2016-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven R. Havlir

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed are a method and a processing device directed to determining global branch history for branch prediction. The method includes shifting first bits of a branch signature into a current global branch history and performing a bitwise exclusive-or (XOR) function on second bits of the branch signature and shifted bits of the current global branch history. In this way, the current global branch history is updated. The processing device implements the method using a shift logic configured to store and shift bits representing a current global branch history, a register configured to store the current global branch history, decision circuitry configured to determine whether or not a branch is taken, and XOR gates.

公开(公告)号：US20180165314A1

公开(公告)日：2018-06-14

申请号：US15824771

申请日：2017-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven R. Havlir ,  Patrick J. Shyvers

IPC: G06F17/30

CPC classification number: G06F16/2264 ,  G06F9/3844 ,  G06F16/2246 ,  G06F16/2255

Abstract: Described herein is a system and method for multiplexer tree (muxtree) indexing. Muxtree indexing performs hashing and row reduction in parallel by use of each select bit only once in a particular path of the muxtree. The muxtree indexing generates a different final index as compared to conventional hashed indexing but still results in a fair hash, where all table entries get used with equal distribution with uniformly random selects.

公开(公告)号：US11579884B2

公开(公告)日：2023-02-14

申请号：US16913520

申请日：2020-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashok Tirupathy Venkatachar ,  Steven R. Havlir ,  Robert B. Cohen

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/1027

Abstract: Techniques for performing instruction fetch operations are provided. The techniques include determining instruction addresses for a primary branch prediction path; requesting that a level 0 translation lookaside buffer (“TLB”) caches address translations for the primary branch prediction path; determining either or both of alternate control flow path instruction addresses and lookahead control flow path instruction addresses; and requesting that either the level 0 TLB or an alternative level TLB caches address translations for either or both of the alternate control flow path instruction addresses and the lookahead control flow path instruction addresses.

公开(公告)号：US11308057B2

公开(公告)日：2022-04-19

申请号：US15824771

申请日：2017-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven R. Havlir ,  Patrick J. Shyvers

IPC: G06F16/22 ,  G06F9/38

Abstract: Described herein is a system and method for multiplexer tree (muxtree) indexing. Muxtree indexing performs hashing and row reduction in parallel by use of each select bit only once in a particular path of the muxtree. The muxtree indexing generates a different final index as compared to conventional hashed indexing but still results in a fair hash, where all table entries get used with equal distribution with uniformly random selects.

公开(公告)号：US10592248B2

公开(公告)日：2020-03-17

申请号：US15252164

申请日：2016-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven R. Havlir

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/0862

Abstract: Techniques for improving branch target buffer (“BTB”) operation. A compressed BTB is included within a branch prediction unit along with an uncompressed BTB. To support prediction of up to two branch instructions per cycle, the uncompressed BTB includes entries that each store data for up to two branch predictions. The compressed BTB includes entries that store data for only a single branch instruction for situations where storing that single branch instruction in the uncompressed BTB would waste space in that buffer. Space would be wasted in the uncompressed BTB due to the fact that, in order to support two branch lookups per cycle, prediction data for two branches must have certain features in common (such as cache line address) in order to be stored together in a single entry.