公开(公告)号：US11995351B2

公开(公告)日：2024-05-28

申请号：US17515976

申请日：2021-11-01

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Joseph L Greathouse ,  Sean Keely ,  Alan D. Smith ,  Anthony Asaro ,  Ling-Ling Wang ,  Milind N Nemlekar ,  Hari Thangirala ,  Felix Kuehling

IPC: G06F3/00 ,  G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/28

Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.

公开(公告)号：US20250068429A1

公开(公告)日：2025-02-27

申请号：US18536982

申请日：2023-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Stephen Junkins ,  Christopher J. Brennan ,  Ian Richard Beaumont ,  Kellie Marks ,  Matthaeus G. Chajdas ,  Max Oberberger ,  Michael John Bedy ,  Michael Mantor ,  Sean Keely

IPC: G06F9/38

Abstract: A Streaming Wave Coalescer (SWC) circuit stores a first set of state values associated with a first subset of threads of a first wave in a bin based on each of the first subset of threads including a first set of instructions to be executed. A second set of state values associated with a second subset of threads of a second wave is stored in the bin based on each of the second subset of threads including the first set of instructions to be executed and based on the first wave and the second wave both being associated with a hard key. A third wave is formed from the threads of the first subset and the second subset and is emitted for execution. As a result of reorganizing the threads and reconstituting a different wave, thread divergence of waves sent for execution is reduced.

公开(公告)号：US20240221284A1

公开(公告)日：2024-07-04

申请号：US18090689

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Sean Keely ,  Daniel James Skinner

IPC: G06T15/06

CPC classification number: G06T15/06 ,  G06T2210/12

Abstract: A technique for performing ray tracing operations is provided. The technique includes determining error bounds for a rotation operation for a ray; selecting a technique for determining whether the ray intersects a bounding box based on the error bounds; and determining whether the ray hits the bounding box based on the selected technique.

公开(公告)号：US20230132931A1

公开(公告)日：2023-05-04

申请号：US17515976

申请日：2021-11-01

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECNOLOGIES ULC

Inventor： Joseph L. Greathouse ,  Sean Keely ,  Alan D. Smith ,  Anthony Asaro ,  Ling-Ling Wang ,  Milind N. Nemlekar ,  Hari Thangirala ,  Felix Kuehling

IPC: G06F3/06 ,  G06F13/28

Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.

公开(公告)号：US20130328876A1

公开(公告)日：2013-12-12

申请号：US13912791

申请日：2013-06-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Sean Keely

IPC: G06T15/06

CPC classification number: G06T15/06 ,  G06T17/005 ,  G06T2210/52

Abstract: Apparatuses, computer readable mediums, and methods of building a k-dimensional tree (kd-tree) are disclosed. The method may include a first processor, for example a graphics processing unit (GPU), selecting a node to split in a depth first manner. The method may include the GPU splitting based on a split plane a node into a left node and a right node. The GPU may assign the left (right) node to the GPU when a number of polygons associated with the left (right) node is above a threshold and otherwise assign the left node to a second processor, for example a central processing unit (CPU). The CPU may build the kd-tree in a depth first manner. The GPU (CPU) may select a next node to split based on a last node assigned to the GPU (CPU) or by selecting a node that is currently in a local memory of the GPU (CPU).

Abstract translation: 公开了装置，计算机可读介质和建立k维树（kd-tree）的方法。 该方法可以包括第一处理器，例如图形处理单元（GPU），以深度第一方式选择要分割的节点。 该方法可以包括基于将节点拆分成左节点和右节点的GPU分割。 当与左（右）节点相关联的多个多边形的数量高于阈值时，GPU可以将左（右）节点分配给GPU，否则将左节点分配给第二处理器，例如中央处理单元（CPU） 。 CPU可以以深度第一方式构建kd-tree。 GPU（CPU）可以基于分配给GPU（CPU）的最后节点或通过选择当前在GPU（CPU）的本地存储器中的节点来选择要分解的下一个节点。