公开(公告)号：US09000806B2

公开(公告)日：2015-04-07

申请号：US13907466

申请日：2013-05-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Dwight K. Elvey ,  Someshwar Gatty

IPC: H03K19/096 ,  H03K19/00 ,  G06F1/32 ,  G06F17/50

CPC classification number: H03K19/096 ,  G06F1/3237 ,  G06F17/505 ,  G06F2217/78 ,  H03K19/0016 ,  Y02D10/128

Abstract: A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.

Abstract translation: 设备可以包括在时钟周期的第二阶段期间被激活的锁存器; 时钟门控组件，用于控制时钟信号何时到达锁存器; 在时钟周期的第一阶段期间激活的目的地存储元件，其中从锁存器到目的地存储元件存在逻辑路径; 以及位于从锁存器到目标存储元件的逻辑路径中的阻塞元件，其中阻塞元件包括作为第一输入的锁存器的输出，以及作为第二输入的时钟门控元件的输出，以及 其中当时钟门控组件未被使能时，阻塞元件防止锁存器的输出值改变，并且当时钟门控元件被使能时不阻止锁存器的输出值改变。