公开(公告)号：US10310015B2

公开(公告)日：2019-06-04

申请号：US13946083

申请日：2013-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Thomas A. Clouqueur ,  Dwight K. Elvey ,  Kamran Zarrineh

IPC: G01R31/28 ,  G01R31/3185

Abstract: An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. A method includes generating a first scan clock signal for loading scan data into at least one flip flop of a first type, generating a second scan clock signal and a third scan clock signal for loading the scan data into at least one flip flop of a second type, and loading a test pattern into a scan chain defined by the at least flip flop of the first type and the at least one flip flop of the second type responsive to the first, second, and third scan clock signals.

公开(公告)号：US09000806B2

公开(公告)日：2015-04-07

申请号：US13907466

申请日：2013-05-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Dwight K. Elvey ,  Someshwar Gatty

IPC: H03K19/096 ,  H03K19/00 ,  G06F1/32 ,  G06F17/50

CPC classification number: H03K19/096 ,  G06F1/3237 ,  G06F17/505 ,  G06F2217/78 ,  H03K19/0016 ,  Y02D10/128

Abstract: A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.

Abstract translation: 设备可以包括在时钟周期的第二阶段期间被激活的锁存器; 时钟门控组件，用于控制时钟信号何时到达锁存器; 在时钟周期的第一阶段期间激活的目的地存储元件，其中从锁存器到目的地存储元件存在逻辑路径; 以及位于从锁存器到目标存储元件的逻辑路径中的阻塞元件，其中阻塞元件包括作为第一输入的锁存器的输出，以及作为第二输入的时钟门控元件的输出，以及 其中当时钟门控组件未被使能时，阻塞元件防止锁存器的输出值改变，并且当时钟门控元件被使能时不阻止锁存器的输出值改变。

公开(公告)号：US20150026532A1

公开(公告)日：2015-01-22

申请号：US13946083

申请日：2013-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Thomas A. Clouqueur ,  Dwight K. Elvey ,  Kamran Zarrineh

IPC: G01R31/3185

CPC classification number: G01R31/318552 ,  G01R31/318541

Abstract: An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. A method includes generating a first scan clock signal for loading scan data into at least one flip flop of a first type, generating a second scan clock signal and a third scan clock signal for loading the scan data into at least one flip flop of a second type, and loading a test pattern into a scan chain defined by the at least flip flop of the first type and the at least one flip flop of the second type responsive to the first, second, and third scan clock signals.

Abstract translation: 集成电路装置包括配置成扫描链的多个触发器。 多个触发器至少包括第一类型的触发器和至少一个第二类触发器。 一种方法包括产生用于将扫描数据加载到第一类型的至少一个触发器中的第一扫描时钟信号，产生第二扫描时钟信号和用于将扫描数据加载到第二扫描时钟信号的至少一个触发器中的第三扫描时钟信号 类型，并且将测试图案加载到由第一类型的至少触发器定义的扫描链中，以及响应于第一，第二和第三扫描时钟信号的第二类型的至少一个触发器。