-
公开(公告)号：US20230178126A1
公开(公告)日：2023-06-08
申请号：US17854924
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Aaron John Nygren , Michael John Litt , Karthik Gopalakrishnan , Tsun Ho Liu
CPC classification number: G11C7/222 , G11C7/1069 , G11C7/1063
Abstract: A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.
-
公开(公告)号：US20240119993A1
公开(公告)日：2024-04-11
申请号：US18390431
申请日：2023-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Aaron John Nygren , Kathik Gopalakrishnan , Tsun Ho Liu
IPC: G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/06
CPC classification number: G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/0604 , G06F3/0659 , G06F3/0671
Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.
-
公开(公告)号：US20230176608A1
公开(公告)日：2023-06-08
申请号：US17850299
申请日：2022-06-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Aaron John Nygren , Karthik Gopalakrishnan , Tsun Ho Liu
Abstract: A memory includes a read clock state machine and a read clock driver circuit. The read clock state machine has a first input for receiving a read command signal, a second input for receiving a read clock mode signal, and an output for providing a drive enable signal. The read clock driver circuit has an output for providing a read clock signal in response to a clock signal when the drive enable signal is active. When the read clock mode signal indicates a read-only mode, the read clock state machine starts toggling the read clock signal during a read preamble period before a data transmission of a first read command, and continues toggling the read clock signal for at least a read postamble period following the data transmission of the first read command.
-
公开(公告)号：US20230178138A1
公开(公告)日：2023-06-08
申请号：US17850499
申请日：2022-06-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Aaron John Nygren , Karthik Gopalakrishnan , Tsun Ho Liu
IPC: G11C11/4076
CPC classification number: G11C11/4076
Abstract: A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.
-
公开(公告)号：US12002541B2
公开(公告)日：2024-06-04
申请号：US17854924
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Aaron John Nygren , Michael John Litt , Karthik Gopalakrishnan , Tsun Ho Liu
IPC: G11C11/4076 , G06F1/08 , G06F1/10 , G11C7/10 , G11C7/22
CPC classification number: G11C7/222 , G11C7/1063 , G11C7/1069 , G06F1/08 , G06F1/10 , G11C11/4076
Abstract: A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.
-
Patent Agency Ranking
公开(公告)号：US11947833B2
公开(公告)日：2024-04-02
申请号：US17845922
申请日：2022-06-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Anwar Kashem , Craig Daniel Eaton , Pouya Najafi Ashtiani , Tsun Ho Liu
IPC: G06F3/06 , G06F18/214
CPC classification number: G06F3/0656 , G06F3/0683 , G06F18/214 , G06F3/0604
Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.
-
公开(公告)号：US20230176786A1
公开(公告)日：2023-06-08
申请号：US17850658
申请日：2022-06-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Aaron John Nygren , Karthik Gopalakrishnan , Tsun Ho Liu
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0671
Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.
-
公开(公告)号：US12243578B2
公开(公告)日：2025-03-04
申请号：US18390431
申请日：2023-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Aaron John Nygren , Karthik Gopalakrishnan , Tsun Ho Liu
IPC: G06F12/00 , G06F1/08 , G06F1/10 , G06F3/06 , G11C11/4076 , G06F1/3234 , G06F1/3237 , G06F13/00
Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.
-
公开(公告)号：US11854602B2
公开(公告)日：2023-12-26
申请号：US17850658
申请日：2022-06-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Aaron John Nygren , Karthik Gopalakrishnan , Tsun Ho Liu
IPC: G06F12/00 , G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/06
CPC classification number: G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/0604 , G06F3/0659 , G06F3/0671
Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.
-
公开(公告)号：US20230409232A1
公开(公告)日：2023-12-21
申请号：US17845922
申请日：2022-06-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Anwar Kashem , Craig Daniel Eaton , Pouya Najafi Ashtiani , Tsun Ho Liu
CPC classification number: G06F3/0656 , G06K9/6256 , G06F3/0683 , G06F3/0604
Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.016 seconds)
