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公开(公告)号：US11854602B2
公开(公告)日：2023-12-26
申请号：US17850658
申请日：2022-06-27
IPC分类号： G06F12/00 , G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/06
CPC分类号： G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/0604 , G06F3/0659 , G06F3/0671
摘要： A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.
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公开(公告)号：US12002541B2
公开(公告)日：2024-06-04
申请号：US17854924
申请日：2022-06-30
IPC分类号： G11C11/4076 , G06F1/08 , G06F1/10 , G11C7/10 , G11C7/22
CPC分类号： G11C7/222 , G11C7/1063 , G11C7/1069 , G06F1/08 , G06F1/10 , G11C11/4076
摘要： A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.
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公开(公告)号：US20240004583A1
公开(公告)日：2024-01-04
申请号：US17854953
申请日：2022-06-30
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0673
摘要： A random-access memory (RAM) includes a plurality of memory banks, a memory channel interface circuit, and a metadata processing circuit. The memory channel interface circuit couples to a memory channel adapted for coupling to a memory controller. The metadata processing circuit is connected to the memory channel interface circuit and receiving a poison bit sent over the memory channel associated with a write command and write data for the write command. The RAM, responsive to the poison bit indicating that the write data is poisoned, stores at least one of: the poison bit and a code indicating a value of the poison bit in a selected memory bank.
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公开(公告)号：US20230176786A1
公开(公告)日：2023-06-08
申请号：US17850658
申请日：2022-06-27
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0671
摘要： A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.
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公开(公告)号：US20240119993A1
公开(公告)日：2024-04-11
申请号：US18390431
申请日：2023-12-20
IPC分类号： G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/06
CPC分类号： G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/0604 , G06F3/0659 , G06F3/0671
摘要： A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.
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公开(公告)号：US20230176608A1
公开(公告)日：2023-06-08
申请号：US17850299
申请日：2022-06-27
摘要： A memory includes a read clock state machine and a read clock driver circuit. The read clock state machine has a first input for receiving a read command signal, a second input for receiving a read clock mode signal, and an output for providing a drive enable signal. The read clock driver circuit has an output for providing a read clock signal in response to a clock signal when the drive enable signal is active. When the read clock mode signal indicates a read-only mode, the read clock state machine starts toggling the read clock signal during a read preamble period before a data transmission of a first read command, and continues toggling the read clock signal for at least a read postamble period following the data transmission of the first read command.
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公开(公告)号：US20230178138A1
公开(公告)日：2023-06-08
申请号：US17850499
申请日：2022-06-27
IPC分类号： G11C11/4076
CPC分类号： G11C11/4076
摘要： A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.
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公开(公告)号：US09508408B2
公开(公告)日：2016-11-29
申请号：US14243283
申请日：2014-04-02
发明人： Ming-Ju Edward Lee , Shadi M. Barakat , Warren Fritz Kruger , Xiaoling Xu , Toan Duc Pham , Aaron John Nygren
IPC分类号： G11C7/00 , G11C7/22 , G06F13/16 , G06F13/42 , G11C11/4076
CPC分类号： G11C7/22 , G06F13/1689 , G06F13/4234 , G11C7/222 , G11C11/4076
摘要： A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.
摘要翻译： 提供了一种用于调整存储器件中的写时序的方法和系统。 例如，该方法可以包括接收数据信号，写时钟信号和参考信号。 该方法还可以包括随时间检测参考信号中的相移。 参考信号的相移可用于调整数据信号和写入时钟信号之间的相位差，其中存储器件基于数据信号和写入时钟信号的调整的写入定时从数据信号中恢复数据 。
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公开(公告)号：US20230178126A1
公开(公告)日：2023-06-08
申请号：US17854924
申请日：2022-06-30
CPC分类号： G11C7/222 , G11C7/1069 , G11C7/1063
摘要： A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.
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公开(公告)号：US20230178121A1
公开(公告)日：2023-06-08
申请号：US17849089
申请日：2022-06-24
发明人： Aaron John Nygren
CPC分类号： G11C7/1039 , G11C7/1063 , G11C7/109 , G11C7/1048 , G11C7/222
摘要： A high-bandwidth dual-inline memory module (HB-DIMM) includes a plurality of memory chips, a plurality of data buffer chips, and a register clock driver (RCD) circuit. The data buffer chips are coupled to respective sets of the memory chips and transmit data from the memory chips over a host bus at a data rate twice that of the memory chips. The RCD circuit includes a host bus interface and a memory interface coupled to the plurality of memory chips. The RCD circuit implements commands received over the host bus by routing command/address (C/A) signals to the memory chips for providing at least two independently addressable pseudo-channels, the RCD circuit addressing each respective pseudo-channel based on a chip identifier (CID) bit derived from the C/A signals.
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