公开(公告)号：US12079490B2

公开(公告)日：2024-09-03

申请号：US17565372

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0673

Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.

公开(公告)号：US11875875B2

公开(公告)日：2024-01-16

申请号：US17564426

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C7/222 ,  G11C5/06 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1093

Abstract: Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.

公开(公告)号：US20230207038A1

公开(公告)日：2023-06-29

申请号：US17564327

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/36

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/1201 ,  G11C29/36

Abstract: Methods and systems are disclosed for training, by a sequencer of a memory interface system, an interface with DRAM. Techniques disclosed comprise scheduling a command sequence, including DRAM commands that are interleaved with one or more CSR commands; executing the scheduled command sequence, wherein the DRAM commands are sent to the DRAM through an internal datapath of the system and the CSR commands are sent to the internal datapath; and training the interface based on exchange of data, carried out by the DRAM commands, including adjustments to an operational parameter associated with the interface.

公开(公告)号：US20240295898A1

公开(公告)日：2024-09-05

申请号：US18663864

申请日：2024-05-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Deepesh John

IPC: G06F1/08 ,  H03K5/00 ,  H03K5/22

CPC classification number: G06F1/08 ,  H03K5/22 ,  H03K2005/00286

Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

公开(公告)号：US11947833B2

公开(公告)日：2024-04-02

申请号：US17845922

申请日：2022-06-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Tsun Ho Liu

IPC: G06F3/06 ,  G06F18/214

CPC classification number: G06F3/0656 ,  G06F3/0683 ,  G06F18/214 ,  G06F3/0604

Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.

公开(公告)号：US20230205433A1

公开(公告)日：2023-06-29

申请号：US17565372

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0655

Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.

公开(公告)号：US20250004662A1

公开(公告)日：2025-01-02

申请号：US18342186

申请日：2023-06-27

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： David Da Wei Lin ,  Ronald Lee Pettyjohn ,  Pouya Najafi Ashtiani ,  Gershom Birk ,  Anwar Parvez Kashem

IPC: G06F3/06

Abstract: In accordance with described techniques for read gate training and tracking, a computing device includes a memory system (e.g., dynamic random access memory (DRAM)) that receives a memory read operation which includes a memory clock that correlates to a physical layer (PHY) clock. The computing device includes a PHY that receives a return data signal from the memory system, where the return data signal includes a returned data strobe that is out-of-phase with respect to the PHY clock. The computing device includes training logic that utilizes edge detection to determine an unknown clocking phase of the returned data strobe with respect to the PHY clock. The computing device also includes tracking logic that utilizes the edge detection to detect a signal drift of the delay signal with respect to the returned data strobe and compensate for the drift.

公开(公告)号：US20240419343A1

公开(公告)日：2024-12-19

申请号：US18820442

申请日：2024-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G06F3/06

Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.

公开(公告)号：US20230197123A1

公开(公告)日：2023-06-22

申请号：US17556958

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Pouya Najafi Ashtiani ,  Craig Daniel Eaton ,  Kedarnath Balakrishnan

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14

CPC classification number: G11C7/1069 ,  G11C7/1096 ,  G11C7/222 ,  G11C5/14

Abstract: A method and apparatus for performing a simulated write in a computer system includes, responsive to a scheduled memory operation determined by a memory controller, sending a simulated write operation to a physical layer circuitry (PHY) to increase circuit power without enabling the output of the PHY until the memory operation begins. Responsive to the memory operation being complete, sending a simulated write operation to the PHY to decrease circuit power.

公开(公告)号：US20240371427A1

公开(公告)日：2024-11-07

申请号：US18310872

申请日：2023-05-02

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Tsun-Ho Liu ,  Anwar Parvez Kashem ,  Pouya Najafi Ashtiani ,  Wei Qing Xie

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4093

Abstract: A memory system includes a memory controller, a physical layer (PHY), and a memory (e.g., DRAM). Data is written to and read from the memory in different manners for different memory technologies, such as using different signals or signal timings for different memory technologies. Various runtime services specific to the memory technology are performed by the PHY rather than the memory controller. Examples of such runtime services include performing a training routine to train or re-train an interface between the PHY and the memory, performing a power management routine (e.g., to put the main memory in a self-refresh mode), and so forth.