公开(公告)号：US10296292B2

公开(公告)日：2019-05-21

申请号：US15298938

申请日：2016-10-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski ,  Wayne Burleson

IPC: G06F7/48 ,  G06F7/72

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

公开(公告)号：US20180121312A1

公开(公告)日：2018-05-03

申请号：US15338172

申请日：2016-10-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski ,  Steven E. Raasch ,  Shomit N. Das ,  Wayne Burleson

IPC: G06F11/34 ,  G06F11/30

CPC classification number: G06F11/008 ,  G06F11/3058 ,  G06F11/3452 ,  Y02D10/34

Abstract: A system and method for managing operating parameters within a system for optimal power and reliability are described. A device includes a functional unit and a corresponding reliability evaluator. The functional unit provides reliability information to one or more reliability monitors, which translate the information to reliability values. The reliability evaluator determines an overall reliability level for the system based on the reliability values. The reliability monitor compares the actual usage values and the expected usage values. When system has maintained a relatively high level of reliability for a given time interval, the reliability evaluator sends an indication to update operating parameters to reduce reliability of the system, which also reduces power consumption for the system.

公开(公告)号：US20180113678A1

公开(公告)日：2018-04-26

申请号：US15298938

申请日：2016-10-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski ,  Wayne Burleson

IPC: G06F7/48

CPC classification number: G06F7/4824 ,  G06F7/729

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

公开(公告)号：US10592207B2

公开(公告)日：2020-03-17

申请号：US16378055

申请日：2019-04-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Greg Sadowski ,  Wayne Burleson

IPC: G06F7/48 ,  G06F7/72

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

公开(公告)号：US20190235838A1

公开(公告)日：2019-08-01

申请号：US16378055

申请日：2019-04-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Greg SADOWSKI ,  Wayne Burleson

IPC: G06F7/48 ,  G06F7/72

CPC classification number: G06F7/4824 ,  G06F7/729

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

公开(公告)号：US10318363B2

公开(公告)日：2019-06-11

申请号：US15338172

申请日：2016-10-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski ,  Steven E. Raasch ,  Shomit N. Das ,  Wayne Burleson

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/34

Abstract: A system and method for managing operating parameters within a system for optimal power and reliability are described. A device includes a functional unit and a corresponding reliability evaluator. The functional unit provides reliability information to one or more reliability monitors, which translate the information to reliability values. The reliability evaluator determines an overall reliability level for the system based on the reliability values. The reliability monitor compares the actual usage values and the expected usage values. When system has maintained a relatively high level of reliability for a given time interval, the reliability evaluator sends an indication to update operating parameters to reduce reliability of the system, which also reduces power consumption for the system.