公开(公告)号：US20220187901A1

公开(公告)日：2022-06-16

申请号：US17687217

申请日：2022-03-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Greg SADOWSKI ,  Ying CHEN

IPC: G06F1/3296 ,  G06F9/50 ,  G06F1/3287

Abstract: An apparatus includes a plurality of registers to store sets of state information that represent a state history of a processing unit. The apparatus also includes a power management advisor (PMA) to generate a signal based on the sets of state information, wherein the signal indicates a probability that a power state transition of the processing unit achieves a target outcome. In some cases, the signal is provided to a power management controller including hardware circuitry that initiates a power state transition of the processing unit based on the signal and inputs to the power management controller that represent a subset of the state information corresponding to a current power state of the processing unit.

公开(公告)号：US20210405722A1

公开(公告)日：2021-12-30

申请号：US17029852

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Greg SADOWSKI ,  Sriram SUNDARAM ,  Stephen KUSHNIR ,  William C. BRANTLEY ,  Michael J. SCHULTE

IPC: G06F1/28 ,  G05F1/625

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

公开(公告)号：US20200073469A1

公开(公告)日：2020-03-05

申请号：US16115420

申请日：2018-08-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Greg SADOWSKI ,  Ying CHEN

IPC: G06F1/32 ,  G06F9/50

Abstract: An apparatus includes a plurality of registers to store sets of state information that represent a state history of a processing unit. The apparatus also includes a power management advisor (PMA) to generate a signal based on the sets of state information, wherein the signal indicates a probability that a power state transition of the processing unit achieves a target outcome. In some cases, the signal is provided to a power management controller including hardware circuitry that initiates a power state transition of the processing unit based on the signal and inputs to the power management controller that represent a subset of the state information corresponding to a current power state of the processing unit.

公开(公告)号：US20240143056A1

公开(公告)日：2024-05-02

申请号：US18218463

申请日：2023-07-05

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ILC

Inventor： Greg SADOWSKI ,  Sriram Sundarm ,  Stephen Kushnir ,  William C. Brantley ,  Michael J. Schulte

IPC: G06F1/28 ,  G05F1/625

CPC classification number: G06F1/28 ,  G05F1/625

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

公开(公告)号：US20190235838A1

公开(公告)日：2019-08-01

申请号：US16378055

申请日：2019-04-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Greg SADOWSKI ,  Wayne Burleson

IPC: G06F7/48 ,  G06F7/72

CPC classification number: G06F7/4824 ,  G06F7/729

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

公开(公告)号：US20150227387A1

公开(公告)日：2015-08-13

申请号：US14175443

申请日：2014-02-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg SADOWSKI

IPC: G06F9/46 ,  G06F1/28

CPC classification number: G06F9/46 ,  G06F1/28 ,  G06F1/3212 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/174 ,  Y02D10/22 ,  Y02D10/24

Abstract: A method and apparatus of adaptive application performance includes a determination of at least one criteria for implementing adaptive application performance measures. Based upon the determination, adaptive application performance measures are implemented.

Abstract translation: 自适应应用性能的方法和装置包括确定用于实施自适应应用性能测量的至少一个标准。 基于确定，实施适应性应用性能测量。