公开(公告)号：US20150067356A1

公开(公告)日：2015-03-05

申请号：US14015369

申请日：2013-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Trichy Ravi ,  Manish Arora ,  William Brantley ,  Srilatha Manne ,  Indrani Paul ,  Michael Schulte

IPC: G06F1/26

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

Abstract: A data processing system includes a plurality of processor resources, a manager, and a power distributor. Each of the plurality of data processor cores is operable at a selected one of a plurality of performance states. The manager assigns each of a plurality of program elements to one of the plurality of processor resources, and synchronizing the program elements using barriers. The power distributor is coupled to the manager and to the plurality of processor resources, and assigns a performance state to each of the plurality of processor resources within an overall power budget, and in response to detecting that a program element assigned to a first processor resource is at a barrier, increases the performance state of a second processor resource that is not at the barrier within the overall power budget.

Abstract translation: 数据处理系统包括多个处理器资源，管理器和功率分配器。 多个数据处理器核心中的每一个可操作在多个执行状态中的选定的一个。 管理器将多个程序元素中的每一个分配给多个处理器资源中的一个，并且使用屏障同步程序元素。 功率分配器耦合到管理器和多个处理器资源，并且在总功率预算内为多个处理器资源中的每一个分配一个性能状态，并且响应于检测到分配给第一处理器资源的程序元件 处于障碍之下，增加在整个功率预算范围内不处于障碍的第二处理器资源的性能状态。