公开(公告)号：US20220414222A1

公开(公告)日：2022-12-29

申请号：US17356776

申请日：2021-06-24

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Gia Phan ,  Ashish Jain ,  Randall Brown

IPC: G06F21/57 ,  G06F21/60 ,  G06F9/46 ,  G06F9/50 ,  G06T1/20

Abstract: A trusted processor saves and restores context and data stored at a frame buffer of a GPU concurrent with initialization of a CPU of the processing system. In response to detecting that the GPU is powering down, the trusted processor accesses the context of the GPU and data stored at a frame buffer of the GPU via a high-speed bus. The trusted processor stores the context and data at a system memory, which maintains the context and data while the GPU is powered down. In response to detecting that the GPU is powering up again, the trusted processor restores the context and data to the GPU, which can be performed concurrently with initialization of the CPU.

公开(公告)号：US12105666B2

公开(公告)日：2024-10-01

申请号：US17234191

申请日：2021-04-19

Applicant: Advanced Micro Devices, Inc. ,  ATI TECHNOLOGIES ULC

Inventor： Shijie Che ,  Wentao Xu ,  Randall Brown ,  Vaibhav Amarayya Hiremath ,  Manuchehr Taghi-Loo

IPC: G06F9/38 ,  G06F15/177 ,  H04L41/0893

CPC classification number: G06F15/177 ,  G06F9/3877 ,  H04L41/0893

Abstract: A computing system may implement a method for creating a first subdomain by configuring one of a first plurality of slave nodes as a first subdomain master node and configuring one or more other slave nodes of the first plurality of slave nodes as first subdomain slave nodes to the first subdomain master node.

公开(公告)号：US20240319781A1

公开(公告)日：2024-09-26

申请号：US18189993

申请日：2023-03-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Randall Brown ,  Ashish Jain

IPC: G06F1/3234 ,  G06F1/3228 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3228 ,  G06F1/3287

Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition. The persistent on-chip memory utilizes synchronous random-access memory that receives a standby power supply reference level that continually supplies a voltage magnitude by not being turned off.

公开(公告)号：US20220335003A1

公开(公告)日：2022-10-20

申请号：US17234191

申请日：2021-04-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Shijie Che ,  Wentao Xu ,  Randall Brown ,  Vaibhav Amarayya Hiremath ,  Manuchehr Taghi-Loo

IPC: G06F15/177 ,  G06F9/50 ,  G06F9/38 ,  H04L29/12

Abstract: A computing system may implement a method for creating a first subdomain by configuring one of a first plurality of slave nodes as a first subdomain master node and configuring one or more other slave nodes of the first plurality of slave nodes as first subdomain slave nodes to the first subdomain master node.

公开(公告)号：US20180165426A1

公开(公告)日：2018-06-14

申请号：US15373214

申请日：2016-12-08

Applicant: ATI Technologies ULC

Inventor： Kathirkamanathan Nadarajah ,  Randall Brown ,  Sergey Blotsky ,  Xing Yue Zhang

IPC: G06F21/10 ,  G06F21/62 ,  G06F21/71

CPC classification number: G06F21/10

Abstract: Systems, apparatuses, and methods for implementing digital rights management using a GPU are disclosed. In one embodiment, a system includes at least a GPU, a security processor, and a memory. The GPU is configured to execute a first portion of a binary and detect that a second portion of the binary is encrypted. The second portion of the binary includes enhanced content that is available for purchase. If the user purchases the enhanced content, a license server generates a token specific to the security processor of the system and conveys the token to the system. Next, the security processor decrypts the second portion of the binary using the token and stores the decrypted second portion of the binary at a memory location accessible by the first processor. Then, the first processor executes the second portion of the binary.

公开(公告)号：US20180165224A1

公开(公告)日：2018-06-14

申请号：US15375593

申请日：2016-12-12

Applicant: ATI Technologies ULC

Inventor： Randall Brown ,  William Ng

IPC: G06F12/14 ,  H04L29/06 ,  H04L9/32

CPC classification number: G06F21/55 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/1052

Abstract: Systems, apparatuses, and methods for implemented secure encrypted virtualization are disclosed. In one embodiment, a system includes at least one or more main processors, a memory, a memory controller, and a security processor. The system is configured to detect a request to provision a guest virtual machine (VM) in a secure environment. The system computes a first integrity check value from the guest VM prior to initiating the guest VM. The system initiates the guest VM responsive to receiving an indication that the first integrity check value is valid. The system encrypts, with a first encryption key, the guest VM stored in the memory. The security processor loads the first encryption key into the memory controller, and the memory controller encrypts the guest VM with the first encryption key.