公开(公告)号：US20180122749A1

公开(公告)日：2018-05-03

申请号：US15340808

申请日：2016-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Chih LEE ,  Chin-Cheng KUO ,  Yung-Hui WANG ,  Wei-Hong LAI ,  Chung-Ting WANG ,  Hsiao-Yen LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81192

Abstract: A semiconductor wafer includes a substrate structure, a first insulation layer, a conductive layer and a second insulation layer. The substrate structure defines a via. The first insulation layer covers a surface of the substrate structure. The first insulation layer extends into the via, covers a lateral wall of the via and exposes a bottom surface at a bottom of the via. The conductive layer covers the first insulation layer and the bottom surface exposed by the first insulation layer. The second insulation layer covers the conductive layer. A warpage of the semiconductor wafer is less than 550 micrometers.