公开(公告)号：US20190295926A1

公开(公告)日：2019-09-26

申请号：US16277826

申请日：2019-02-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung Hao CHEN ,  Chin-Cheng KUO

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  B81B7/00 ,  B81B7/02

Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.

公开(公告)号：US20210379590A1

公开(公告)日：2021-12-09

申请号：US16893150

申请日：2020-06-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsiao-Yen LEE ,  Ying-Te OU ,  Chin-Cheng KUO ,  Chung Hao CHEN

IPC: B01L3/00 ,  H01L23/538

Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.

公开(公告)号：US20220384309A1

公开(公告)日：2022-12-01

申请号：US17334569

申请日：2021-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yuan KUNG ,  Hung-Yi LIN ,  Chin-Cheng KUO ,  Wu Chou HSU

IPC: H01L23/48 ,  H01L21/768

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.

公开(公告)号：US20220384310A1

公开(公告)日：2022-12-01

申请号：US17334571

申请日：2021-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Cheng KUO

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, a conductive structure and at least one via structure. The conductive structure is disposed on an upper surface of the semiconductor substrate. The at least one via structure is disposed in the semiconductor substrate. A portion of the at least one via structure extends beyond the conductive structure.

公开(公告)号：US20170287863A1

公开(公告)日：2017-10-05

申请号：US15628485

申请日：2017-06-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Cheng KUO ,  Ying-Te OU ,  Lu-Ming LAI

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L24/13 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/10156 ,  H01L2924/00014

Abstract: A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad.

公开(公告)号：US20210082788A1

公开(公告)日：2021-03-18

申请号：US17107585

申请日：2020-11-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung Hao CHEN ,  Chin-Cheng KUO

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  B81B7/00 ,  B81B7/02

Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.

公开(公告)号：US20190055118A1

公开(公告)日：2019-02-21

申请号：US15680056

申请日：2017-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Cheng-Yuan KUNG ,  Che-Hau HUANG ,  Chin-Cheng KUO

IPC: B81B7/00 ,  B81C1/00

Abstract: A Micro Electro-Mechanical System (MEMS) device package includes a first circuit layer, a partition wall, a MEMS component, a second circuit layer and a polymeric dielectric layer. The partition wall is disposed over the first circuit layer. The MEMS component is disposed over the partition wall and electrically connected to the first circuit layer. The first circuit layer, the partition wall and the MEMS component enclose a space. The second circuit layer is disposed over and electrically connected to the first circuit layer. The polymeric dielectric layer is disposed between the first circuit layer and the second circuit layer.

公开(公告)号：US20180122749A1

公开(公告)日：2018-05-03

申请号：US15340808

申请日：2016-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Chih LEE ,  Chin-Cheng KUO ,  Yung-Hui WANG ,  Wei-Hong LAI ,  Chung-Ting WANG ,  Hsiao-Yen LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81192

Abstract: A semiconductor wafer includes a substrate structure, a first insulation layer, a conductive layer and a second insulation layer. The substrate structure defines a via. The first insulation layer covers a surface of the substrate structure. The first insulation layer extends into the via, covers a lateral wall of the via and exposes a bottom surface at a bottom of the via. The conductive layer covers the first insulation layer and the bottom surface exposed by the first insulation layer. The second insulation layer covers the conductive layer. A warpage of the semiconductor wafer is less than 550 micrometers.

公开(公告)号：US20170365515A1

公开(公告)日：2017-12-21

申请号：US15184828

申请日：2016-06-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Cheng KUO ,  Pao-Nan LEE ,  Chih-Pin HUNG ,  Ying-Te OU

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5286 ,  H01L24/02 ,  H01L24/05 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05562

Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.