公开(公告)号：US20200296836A1

公开(公告)日：2020-09-17

申请号：US16351026

申请日：2019-03-12

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yu-Ju LIAO ,  Chien-Fan CHEN ,  Chien-Hao WANG ,  I-Chia LIN

IPC: H05K1/18 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 μm and 351 μm.

公开(公告)号：US20180158783A1

公开(公告)日：2018-06-07

申请号：US15871805

申请日：2018-01-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： I-Chia LIN ,  Chieh-Chen FU ,  Kuo Hsien LIAO ,  Cheng-Nan LIN

IPC: H01L23/552

Abstract: A semiconductor device package includes: (1) a carrier; (2) an electronic component disposed over a top surface of the carrier; (3) a package body disposed over the top surface of the carrier and covering the electronic component; and (4) a shield layer, including a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer. The first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer. A permeability of the first electrically conductive layer is different from a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer.

公开(公告)号：US20170200682A1

公开(公告)日：2017-07-13

申请号：US14990366

申请日：2016-01-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： I-Chia LIN ,  Chieh-Chen FU ,  Kuo Hsien LIAO ,  Cheng-Nan LIN

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81

Abstract: A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top surface of the carrier and covering the electronic component. The semiconductor device package further includes a shield layer, which in turn includes a first electrically conductive layer, a first magnetically permeable layer, and a second electrically conductive layer, where the first magnetically permeable layer is interposed between and directly contacts the first electrically conductive layer and the second electrically conductive layer.