公开(公告)号：US20170005042A1

公开(公告)日：2017-01-05

申请号：US14791043

申请日：2015-07-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shih-Ren CHEN ,  Cheng-Nan LIN

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00012

Abstract: The present disclosure relates to a semiconductor device package and a method for manufacturing the semiconductor device package. The semiconductor device package includes a substrate, a grounding element, a component, a package body and a conductive layer. The grounding element is disposed in the substrate and includes a connection surface exposed at a second portion of a lateral surface of the substrate. The component is disposed on a top surface of the substrate. The package body covers the component and the top surface of the substrate. A lateral surface of the package body is aligned with the lateral surface of the substrate. The conductive layer covers a top surface and the lateral surface of the package body, and further covers the second portion of the lateral surface of the substrate. A first portion of the lateral surface of the substrate is exposed from the conductive layer.

Abstract translation: 本发明涉及半导体器件封装以及半导体器件封装的制造方法。 半导体器件封装包括衬底，接地元件，部件，封装体和导电层。 接地元件设置在基板中，并且包括暴露在基板的侧表面的第二部分处的连接表面。 该部件设置在基板的顶表面上。 封装体覆盖基板的部件和顶表面。 封装体的侧表面与衬底的侧表面对齐。 导电层覆盖封装主体的顶表面和侧表面，并且还覆盖基板的侧表面的第二部分。 衬底的侧表面的第一部分从导电层露出。