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公开(公告)号:US20160218021A1
公开(公告)日:2016-07-28
申请号:US14606138
申请日:2015-01-27
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Bernd Karl APPELT , Kay Stefan ESSIG , William T. CHEN , Yuan-Chang SU
IPC: H01L21/56 , H01L25/00 , H01L21/48 , H01L25/065 , H01L23/498 , H01L23/31
CPC classification number: H01L21/568 , H01L21/4832 , H01L21/4857 , H01L23/3107 , H01L23/49541 , H01L23/49582 , H01L23/49816 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/05599 , H01L2224/13101 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/16245 , H01L2224/32145 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/81444 , H01L2224/85444 , H01L2225/06513 , H01L2924/00014 , H01L2924/0002 , H01L2924/014 , H01L2924/181 , H01L2924/00012 , H01L2924/00
Abstract: The present disclosure relates to a semiconductor package and method of manufacturing the same. The semiconductor package includes a first die, a plurality of conductive pads, a package body and a plurality of first traces. The plurality of conductive pads electrically connect to the first die, and each of the plurality of conductive pads has a lower surface. The package body encapsulates the first die and the plurality of conductive pads and exposes the lower surface of each of the plurality of conductive pads from a lower surface of the package body. The plurality of first traces are disposed on the lower surface of the package body and are connected to the lower surface of each of the plurality of conductive pads. A thickness of each of the plurality of first traces is less than 100 μm.
Abstract translation: 本公开涉及一种半导体封装及其制造方法。 半导体封装包括第一裸片,多个导电焊盘,封装主体和多个第一迹线。 多个导电焊盘电连接到第一管芯,并且多个导电焊盘中的每一个具有下表面。 封装体封装第一管芯和多个导电焊盘,并且从封装体的下表面暴露多个导电焊盘中的每一个的下表面。 多个第一迹线设置在封装主体的下表面上并且连接到多个导电焊盘中的每一个的下表面。 多个第一迹线中的每一个的厚度小于100μm。
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公开(公告)号:US20190103386A1
公开(公告)日:2019-04-04
申请号:US15721257
申请日:2017-09-29
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: William T. CHEN , John Richard HUNT , Chih-Pin HUNG , Chen-Chao WANG , Chih-Yi HUANG
IPC: H01L25/10 , H01L23/538 , H01L23/31 , H01L23/367 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/00 , H01L25/00
Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.
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公开(公告)号:US20190088506A1
公开(公告)日:2019-03-21
申请号:US16182589
申请日:2018-11-06
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Bernd Karl APPELT , Kay Stefan ESSIG , William T. CHEN , Yuan-Chang SU
IPC: H01L21/56 , H01L23/498 , H01L25/00 , H01L25/065 , H01L23/31 , H01L23/495 , H01L21/48 , H01L23/00
Abstract: A semiconductor package includes: (1) a first die; (2) conductive pads electrically connected to the first die, and each of the conductive pads having a lower surface; (3) a package body encapsulating the first die and the conductive pads and exposing the lower surface of each of the conductive pads from a lower surface of the package body; and (4) first traces disposed on the lower surface of the package body and connected to the lower surface of each of the conductive pads, wherein a thickness of each of the first traces is less than 100 micrometers.
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