公开(公告)号：US20250029951A1

公开(公告)日：2025-01-23

申请号：US18223528

申请日：2023-07-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kay Stefan ESSIG ,  You-Lung YEN ,  Bernd Karl APPELT

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/552 ,  H01L23/66 ,  H01L25/16

Abstract: An electronic device is provided. The electronic device includes a first electronic component, a plurality of second electronic components, and a plurality of conductive elements. The plurality of second electronic components are disposed under the first electronic component. The plurality of conductive elements electrically connect the first electronic component to the plurality of second electronic components. The plurality of conductive elements are free from vertically overlapping the plurality of second electronic components.

公开(公告)号：US20210225746A1

公开(公告)日：2021-07-22

申请号：US17221597

申请日：2021-04-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT ,  You-Lung YEN ,  Kay Stefan ESSIG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.

公开(公告)号：US20210028150A1

公开(公告)日：2021-01-28

申请号：US16523787

申请日：2019-07-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.

公开(公告)号：US20200350180A1

公开(公告)日：2020-11-05

申请号：US16403393

申请日：2019-05-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/552 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/52

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and a second surface opposite to the first surface, an encapsulant, and an antenna. The encapsulant is disposed on the first surface of the carrier. The antenna is disposed on the encapsulant. The antenna includes a seed layer and a conductive layer.

公开(公告)号：US20180019221A1

公开(公告)日：2018-01-18

申请号：US15649545

申请日：2017-07-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT ,  Kay Stefan ESSIG ,  Chi-Tsung CHIU

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/2518 ,  H01L2224/32146 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/01022 ,  H01L2924/01029

Abstract: A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

公开(公告)号：US20220367384A1

公开(公告)日：2022-11-17

申请号：US17321139

申请日：2021-05-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L23/433

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.

公开(公告)号：US20220115288A1

公开(公告)日：2022-04-14

申请号：US17066407

申请日：2020-10-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A substrate structure, a semiconductor package structure including the same and a method for manufacturing the same are provided. The substrate structure includes a first passivation layer, a first circuit layer and a first protection layer. The first passivation layer has a first surface and a second surface opposite to the first surface. The first circuit layer has an outer lateral surface. A first portion of the first circuit layer is disposed in the first passivation layer. The first protection layer is disposed on a second portion of the first circuit layer and exposed from the first surface of the first passivation layer. The outer lateral surface of the first circuit layer is covered by the first passivation layer or the first protection layer.

公开(公告)号：US20220020605A1

公开(公告)日：2022-01-20

申请号：US16933813

申请日：2020-07-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kay Stefan ESSIG ,  Jean Marc YANNOU ,  Bradford FACTOR

IPC: H01L21/56 ,  H01L23/492 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a conductive base, a first semiconductor die, a first conductive pillar, and a first encapsulant. The conductive base has a first surface. The first semiconductor die is disposed on the first surface of the conductive base. The first conductive pillar is disposed on the first semiconductor die. The first encapsulant is disposed on the first surface of the conductive base. The first encapsulant encapsulates the first semiconductor die. The first encapsulant includes an opening defined by the first conductive pillar.

公开(公告)号：US20160218021A1

公开(公告)日：2016-07-28

申请号：US14606138

申请日：2015-01-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT ,  Kay Stefan ESSIG ,  William T. CHEN ,  Yuan-Chang SU

IPC: H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/4857 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/13101 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81444 ,  H01L2224/85444 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor package and method of manufacturing the same. The semiconductor package includes a first die, a plurality of conductive pads, a package body and a plurality of first traces. The plurality of conductive pads electrically connect to the first die, and each of the plurality of conductive pads has a lower surface. The package body encapsulates the first die and the plurality of conductive pads and exposes the lower surface of each of the plurality of conductive pads from a lower surface of the package body. The plurality of first traces are disposed on the lower surface of the package body and are connected to the lower surface of each of the plurality of conductive pads. A thickness of each of the plurality of first traces is less than 100 μm.

Abstract translation: 本公开涉及一种半导体封装及其制造方法。 半导体封装包括第一裸片，多个导电焊盘，封装主体和多个第一迹线。 多个导电焊盘电连接到第一管芯，并且多个导电焊盘中的每一个具有下表面。 封装体封装第一管芯和多个导电焊盘，并且从封装体的下表面暴露多个导电焊盘中的每一个的下表面。 多个第一迹线设置在封装主体的下表面上并且连接到多个导电焊盘中的每一个的下表面。 多个第一迹线中的每一个的厚度小于100μm。

公开(公告)号：US20220328416A1

公开(公告)日：2022-10-13

申请号：US17225832

申请日：2021-04-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.