公开(公告)号：US20160218021A1

公开(公告)日：2016-07-28

申请号：US14606138

申请日：2015-01-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT ,  Kay Stefan ESSIG ,  William T. CHEN ,  Yuan-Chang SU

IPC: H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/4857 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/13101 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81444 ,  H01L2224/85444 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor package and method of manufacturing the same. The semiconductor package includes a first die, a plurality of conductive pads, a package body and a plurality of first traces. The plurality of conductive pads electrically connect to the first die, and each of the plurality of conductive pads has a lower surface. The package body encapsulates the first die and the plurality of conductive pads and exposes the lower surface of each of the plurality of conductive pads from a lower surface of the package body. The plurality of first traces are disposed on the lower surface of the package body and are connected to the lower surface of each of the plurality of conductive pads. A thickness of each of the plurality of first traces is less than 100 μm.

Abstract translation: 本公开涉及一种半导体封装及其制造方法。 半导体封装包括第一裸片，多个导电焊盘，封装主体和多个第一迹线。 多个导电焊盘电连接到第一管芯，并且多个导电焊盘中的每一个具有下表面。 封装体封装第一管芯和多个导电焊盘，并且从封装体的下表面暴露多个导电焊盘中的每一个的下表面。 多个第一迹线设置在封装主体的下表面上并且连接到多个导电焊盘中的每一个的下表面。 多个第一迹线中的每一个的厚度小于100μm。

公开(公告)号：US20190067211A1

公开(公告)日：2019-02-28

申请号：US15691053

申请日：2017-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng LEE ,  Yuan-Chang SU

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2221/68345 ,  H01L2221/68359 ,  H05K1/0284 ,  H05K1/0313 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/111 ,  H05K1/113 ,  H05K1/119

Abstract: A substrate for packaging a semiconductor device is disclosed. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer. The first dielectric layer includes a first portion adjacent to the first surface, a second portion adjacent to the second surface, and a reinforcement structure between the first portion and the second portion. A thickness of the first portion of the first dielectric layer is different from a thickness of the second portion of the first dielectric layer.

公开(公告)号：US20180240743A1

公开(公告)日：2018-08-23

申请号：US15439752

申请日：2017-02-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih Cheng LEE ,  Yuan-Chang SU

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/00012

Abstract: A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.

公开(公告)号：US20170229402A1

公开(公告)日：2017-08-10

申请号：US15495282

申请日：2017-04-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Chih-Cheng LEE ,  Yuan-Chang SU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/544 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/3512

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

公开(公告)号：US20160315041A1

公开(公告)日：2016-10-27

申请号：US14696355

申请日：2015-04-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Chih-Cheng LEE ,  Yuan-Chang SU

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/683 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68345 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/73204

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

Abstract translation: 插入器基板包括嵌入电介质层的第一表面的第一电路图案和嵌入电介质层的第二表面的第二电路图案; 在所述第一电路图案和所述第二电路图案之间的介电层中的中间图案化导电层; 第一导电通孔，其中每个第一导电通孔包括与第一电路图案相邻的第一端和与中间图案化导电层相邻的第二端，其中第一端的宽度大于第二端的宽度; 第二导电通孔，其中每个第二导电通孔包括与第二电路图案相邻的第三端和与中间图案化导电层相邻的第四端，其中第三端的宽度大于第四端的宽度。

公开(公告)号：US20160218019A1

公开(公告)日：2016-07-28

申请号：US15088683

申请日：2016-04-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang SU ,  Shih-Fu HUANG ,  Chia-Cheng CHEN

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/27013 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.

Abstract translation: 包装载体包括：（1）电介质层; （2）第一导电图案，其嵌入在所述电介质层中并且邻近所述电介质层的第一表面设置，并且包括多个第一焊盘; （3）延伸穿过介电层的多个第一导电柱，其中每个第一导电柱包括连接到至少一个第一焊盘的第一导电柱段和连接到第一导电柱段的第二导电柱段 第一导电柱段和第一导电柱段的横向范围不同于第二导电柱段的横向范围; 以及（4）第二导电图案，其邻近所述电介质层的第二表面设置，并且包括连接到所述第二导电柱段中的相应一个的多个第二焊盘。

公开(公告)号：US20160143149A1

公开(公告)日：2016-05-19

申请号：US14548118

申请日：2014-11-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang SU ,  Chih-Cheng LEE ,  Cheng-Lin HO

IPC: H05K1/18 ,  H01L21/48 ,  H05K3/18 ,  H05K3/46 ,  H05K3/10 ,  H01L23/498 ,  H05K3/30

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/188 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

Abstract translation: 公开了半导体封装结构和制造方法。 半导体封装结构包括第一电介质层，第二电介质层，部件，图案化导电层和至少两个导电通孔。 第一电介质层具有与第一表面相对的第一表面和第二表面。 第二电介质层具有与第一表面相对的第一表面和第二表面。 第一电介质层的第二表面附着到第二电介质层的第一表面。 第二电介质层内的部件具有与第一电介质层的第二表面相邻的至少两个电触点。 第一介电层内的图案化导电层与第一介电层的第一表面相邻。 导电通孔穿透第一电介质层并将电触点与图案化的导电层电连接。

公开(公告)号：US20220359361A1

公开(公告)日：2022-11-10

申请号：US17873085

申请日：2022-07-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che LEE ,  Ming-Chiang LEE ,  Yuan-Chang SU ,  Tien-Szu CHEN ,  Chih-Cheng LEE ,  You-Lung YEN

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H01L21/48

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

公开(公告)号：US20190088506A1

公开(公告)日：2019-03-21

申请号：US16182589

申请日：2018-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bernd Karl APPELT ,  Kay Stefan ESSIG ,  William T. CHEN ,  Yuan-Chang SU

IPC: H01L21/56 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes: (1) a first die; (2) conductive pads electrically connected to the first die, and each of the conductive pads having a lower surface; (3) a package body encapsulating the first die and the conductive pads and exposing the lower surface of each of the conductive pads from a lower surface of the package body; and (4) first traces disposed on the lower surface of the package body and connected to the lower surface of each of the conductive pads, wherein a thickness of each of the first traces is less than 100 micrometers.

公开(公告)号：US20190080995A1

公开(公告)日：2019-03-14

申请号：US15699816

申请日：2017-09-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng LEE ,  Yuan-Chang SU

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683

Abstract: A substrate for packaging a semiconductor device includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer. The first patterned conductive layer includes a first portion and a second portion. Each of the first portion and the second portion is embedded in the first dielectric layer and protrudes relative to the first surface of the first dielectric layer toward a direction away from the second surface of the first dielectric layer. A thickness of the first portion of the first patterned conductive layer is greater than a thickness of the second portion of the first patterned conductive layer.