DOUBLE SIDE VIA LAST METHOD FOR DOUBLE EMBEDDED PATTERNED SUBSTRATE
    5.
    发明申请
    DOUBLE SIDE VIA LAST METHOD FOR DOUBLE EMBEDDED PATTERNED SUBSTRATE 有权
    双面嵌入式图案的双面方法

    公开(公告)号:US20160315041A1

    公开(公告)日:2016-10-27

    申请号:US14696355

    申请日:2015-04-24

    Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

    Abstract translation: 插入器基板包括嵌入电介质层的第一表面的第一电路图案和嵌入电介质层的第二表面的第二电路图案; 在所述第一电路图案和所述第二电路图案之间的介电层中的中间图案化导电层; 第一导电通孔,其中每个第一导电通孔包括与第一电路图案相邻的第一端和与中间图案化导电层相邻的第二端,其中第一端的宽度大于第二端的宽度; 第二导电通孔,其中每个第二导电通孔包括与第二电路图案相邻的第三端和与中间图案化导电层相邻的第四端,其中第三端的宽度大于第四端的宽度。

    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS
    7.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS 有权
    半导体封装结构与半导体工艺

    公开(公告)号:US20160143149A1

    公开(公告)日:2016-05-19

    申请号:US14548118

    申请日:2014-11-19

    Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

    Abstract translation: 公开了半导体封装结构和制造方法。 半导体封装结构包括第一电介质层,第二电介质层,部件,图案化导电层和至少两个导电通孔。 第一电介质层具有与第一表面相对的第一表面和第二表面。 第二电介质层具有与第一表面相对的第一表面和第二表面。 第一电介质层的第二表面附着到第二电介质层的第一表面。 第二电介质层内的部件具有与第一电介质层的第二表面相邻的至少两个电触点。 第一介电层内的图案化导电层与第一介电层的第一表面相邻。 导电通孔穿透第一电介质层并将电触点与图案化的导电层电连接。

    SUBSTRATE FOR PACKAGING A SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20190080995A1

    公开(公告)日:2019-03-14

    申请号:US15699816

    申请日:2017-09-08

    Abstract: A substrate for packaging a semiconductor device includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer and electrically connected to the first patterned conductive layer. The first patterned conductive layer includes a first portion and a second portion. Each of the first portion and the second portion is embedded in the first dielectric layer and protrudes relative to the first surface of the first dielectric layer toward a direction away from the second surface of the first dielectric layer. A thickness of the first portion of the first patterned conductive layer is greater than a thickness of the second portion of the first patterned conductive layer.

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