公开(公告)号：US20080018572A1

公开(公告)日：2008-01-24

申请号：US11685853

申请日：2007-03-14

Applicant: Ae Shin ,  Jin Jeon

Inventor： Ae Shin ,  Jin Jeon

IPC: G09G3/36

CPC classification number: G02F1/1345 ,  G02F1/13452

Abstract: A display substrate includes gate lines, driving circuit part, signal lines, connection lines and a contact part. Gate lines are formed on a display area and intersect data lines. Driving circuit part is formed on a peripheral area surrounding the display area and provides a gate signal to the gate lines. Signal lines are formed adjacent to the driving circuit part and provide a driving signal to the driving circuit part. Connection lines include a first end portion overlapped the signal lines and a second end portion electrically connected with the driving circuit part. A contact part is formed on the signal lines and connects the first end portion with the signal lines.

Abstract translation: 显示基板包括栅线，驱动电路部分，信号线，连接线和接触部。 栅极线形成在显示区域上并与数据线相交。 驱动电路部分形成在显示区域周围的周边区域上，并向栅极线提供栅极信号。 信号线与驱动电路部分相邻地形成，并向驱动电路部分提供驱动信号。 连接线包括与信号线重叠的第一端部分和与驱动电路部分电连接的第二端部分。 在信号线上形成接触部分，并将第一端部与信号线连接起来。

公开(公告)号：US20080088555A1

公开(公告)日：2008-04-17

申请号：US11870041

申请日：2007-10-10

Applicant: Ae Shin ,  Jin Jeon ,  Kee-Han Uh ,  Jin-Young Choi

Inventor： Ae Shin ,  Jin Jeon ,  Kee-Han Uh ,  Jin-Young Choi

IPC: G09G3/36 ,  H03K3/00

CPC classification number: G09G3/3677 ,  G09G3/2092 ,  G09G2360/18 ,  G11C19/28 ,  H03K17/16 ,  H03K17/687

Abstract: A gate driving circuit includes a shift resister having stages cascade-connected to one another. Each stage includes a pull-up part, a first pull-up driving part, a first pull-down part and a first ripple prevention part. The pull-up part outputs a high value of a first clock signal to a first output terminal. The first pull-up driving part applies a low value to a control electrode of the pull-up part to turn off the pull-up part. The first pull-down part applies the low value to the signal outputted to the first output terminal. The first ripple prevention part applies the low value of the first input signal to the control electrode of the pull-up part to turn off the pull-up part, and prevents ripple from occurring at the control electrode of the pull-up part. Thus, an abnormal gate-on signal is prevented, to reduce driving malfunction of a display apparatus.

Abstract translation: 门驱动电路包括具有彼此级联的级的移位寄存器。 每个级包括上拉部分，第一上拉驱动部分，第一下拉部分和第一纹波防止部分。 上拉部分将第一时钟信号的高值输出到第一输出端子。 第一上拉驱动部分将低值施加到上拉部分的控制电极以关闭上拉部分。 第一下拉部分对输出到第一输出端子的信号施加低值。 第一纹波防止部分将第一输入信号的低值施加到上拉部分的控制电极以关闭上拉部分，并且防止在上拉部分的控制电极处发生纹波。 因此，防止异常导通信号，以减少显示装置的驱动故障。

公开(公告)号：US07139043B2

公开(公告)日：2006-11-21

申请号：US10961240

申请日：2004-10-07

Applicant: Een-Mi Kwon ,  Ae Shin ,  Seung-Soo Baek ,  Young-Mi Tak

Inventor： Een-Mi Kwon ,  Ae Shin ,  Seung-Soo Baek ,  Young-Mi Tak

IPC: G02F1/1343

CPC classification number: G02F1/134336 ,  G02F1/133707 ,  G02F1/1393

Abstract: A thin film transistor array panel is provided, which includes: a substrate; a gate line formed on the substrate; first and second storage electrodes formed on the substrate and disposed opposite each other with respect to the gate line; a gate insulating layer formed in the gate line and the first and the second storage electrodes; a curved data line formed on the gate insulating layer; a thin film transistor connected to the gate line and the data line; a passivation layer formed on the data line and the thin film transistor; a pixel electrode formed on the passivation layer, connected to the thin film transistor, and having an obtuse corner and an acute corner; and an overpass cross over the gate line and connected to the first and the second storage electrodes.

Abstract translation: 提供薄膜晶体管阵列面板，其包括：基板; 形成在基板上的栅极线; 第一和第二存储电极，其形成在所述基板上并且相对于所述栅极线相对设置; 栅极绝缘层，形成在栅极线和第一和第二存储电极中; 形成在所述栅绝缘层上的弯曲数据线; 连接到栅极线和数据线的薄膜晶体管; 形成在数据线和薄膜晶体管上的钝化层; 形成在钝化层上的像素电极，连接到薄膜晶体管，并具有钝角和锐角; 并且跨越栅极线并且连接到第一和第二存储电极的立交桥。

公开(公告)号：US20050128415A1

公开(公告)日：2005-06-16

申请号：US10961240

申请日：2004-10-07

Applicant: Een-Mi Kwon ,  Ae Shin ,  Seung-Soo Baek ,  Young-Mi Tak

Inventor： Een-Mi Kwon ,  Ae Shin ,  Seung-Soo Baek ,  Young-Mi Tak

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/136 ,  G02F1/139 ,  H01L21/77 ,  H01L27/02 ,  H01L29/786

CPC classification number: G02F1/134336 ,  G02F1/133707 ,  G02F1/1393

Abstract: A thin film transistor array panel is provided, which includes: a substrate; a gate line formed on the substrate; first and second storage electrodes formed on the substrate and disposed opposite each other with respect to the gate line; a gate insulating layer formed in the gate line and the first and the second storage electrodes; a curved data line formed on the gate insulating layer; a thin film transistor connected to the gate line and the data line; a passivation layer formed on the data line and the thin film transistor; a pixel electrode formed on the passivation layer, connected to the thin film transistor, and having an obtuse corner and an acute corner; and an overpass cross over the gate line and connected to the first and the second storage electrodes.

Abstract translation: 提供薄膜晶体管阵列面板，其包括：基板; 形成在基板上的栅极线; 第一和第二存储电极，其形成在所述基板上并且相对于所述栅极线彼此相对设置; 栅极绝缘层，形成在栅极线和第一和第二存储电极中; 形成在所述栅绝缘层上的弯曲数据线; 连接到栅极线和数据线的薄膜晶体管; 形成在数据线和薄膜晶体管上的钝化层; 形成在钝化层上的像素电极，连接到薄膜晶体管，并具有钝角和锐角; 并且跨越栅极线并且连接到第一和第二存储电极的立交桥。

公开(公告)号：US07700952B2

公开(公告)日：2010-04-20

申请号：US11733985

申请日：2007-04-11

Applicant: Yong Han Park ,  Kee Han Uh ,  Ae Shin ,  Yong Koo Her

Inventor： Yong Han Park ,  Kee Han Uh ,  Ae Shin ,  Yong Koo Her

IPC: H01L29/04 ,  H01L31/036 ,  H01L23/48 ,  H01L23/52

CPC classification number: G02F1/1345 ,  H01L27/12 ,  H01L27/124

Abstract: A contact pad is disclosed including a first electrode pattern with an open portion inside, an insulation layer formed on the first electrode pattern and having a contact via portion formed therein, and a second electrode pattern formed on the insulation layer and electrically connected to the first electrode pattern through the contact via portion. The second electrode pattern comprises single electrode patterns spaced apart from one another. A thin film transistor substrate and a liquid crystal display panel having the contact pad are also disclosed.

Abstract translation: 公开了一种接触垫，其包括内部具有开放部分的第一电极图案，形成在第一电极图案上并具有形成在其中的接触通孔部分的绝缘层，以及形成在绝缘层上并电连接到第一电极图案的第二电极图案 电极图案通过接触通孔部分。 第二电极图案包括彼此间隔开的单个电极图案。 还公开了具有接触焊盘的薄膜晶体管基板和液晶显示面板。

公开(公告)号：US20100066963A1

公开(公告)日：2010-03-18

申请号：US12560927

申请日：2009-09-16

Applicant: Jaehoon HWANG ,  Yong-Kyu Jang ,  Sang-Woo Kim ,  Ae Shin ,  Chang-Woo Shim

Inventor： Jaehoon HWANG ,  Yong-Kyu Jang ,  Sang-Woo Kim ,  Ae Shin ,  Chang-Woo Shim

IPC: G02F1/1343

CPC classification number: G02F1/134336 ,  G02F1/133707 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2001/134372 ,  G02F2201/14

Abstract: A display device having a gate line on a first substrate, a gate insulating layer covering the gate line, a semiconductor layer on the gate insulating layer, a data line intersecting the gate line and including a source electrode and a drain electrode facing the source electrode on the semiconductor layer, a connection assistant separated from the data line, a passivation layer covering the data line and including contact holes exposing the connection assistant and a pixel electrode, including a plurality of sub-pixel electrodes, and formed on the passivation layer. The sub-pixel electrodes are electrically connected to each other through the connection assistant and at least one of the sub-pixel electrodes is electrically connected to the drain electrode. The connection assistant is connected to facing edges of adjacent sub-pixel electrodes and is disposed at about ¼ the distance from the end of the left or the right side of the sub-pixel electrode.

Abstract translation: 一种在第一基板上具有栅极线的显示装置，覆盖栅极线的栅极绝缘层，栅极绝缘层上的半导体层，与栅极线相交的数据线，并且包括面对源极的源电极和漏电极 在半导体层上，与数据线分离的连接助手，覆盖数据线的钝化层，并且包括暴露连接助手的接触孔和包括多个子像素电极的像素电极，并形成在钝化层上。 子像素电极通过连接辅助电路彼此电连接，并且至少一个子像素电极电连接到漏电极。 连接辅助件连接到相邻的子像素电极的相对边缘，并且设置在离子像素电极的左侧或右侧的距离大约1/4的距离处。

公开(公告)号：US08049699B2

公开(公告)日：2011-11-01

申请号：US11349301

申请日：2006-02-07

Applicant: Ae Shin ,  Dong-Gyu Kim

Inventor： Ae Shin ,  Dong-Gyu Kim

IPC: G09G3/36

CPC classification number: G09G3/3607 ,  G02F1/136213 ,  G02F2001/134345 ,  G09G3/3655 ,  G09G2310/021 ,  G09G2310/0248 ,  G09G2320/028 ,  G09G2320/0673

Abstract: A liquid crystal display apparatus includes a plurality of pixel electrodes arrayed in a matrix, each pixel electrode of the plurality of pixel electrodes having first and second sub-pixel electrodes. The apparatus further includes a plurality of first switching devices connected to the first sub-pixel electrodes, a plurality of gate lines connected to the switching devices, a plurality of data lines connected to the first devices and passing between the pixel electrodes to transmit data voltages, and first and second storage electrodes disposed between the pixel electrodes and the data lines disposed at both sides of the pixel electrodes and overlapping the first sub-pixel electrodes.

Abstract translation: 液晶显示装置包括以矩阵排列的多个像素电极，多个像素电极中的每个像素电极具有第一和第二子像素电极。 该装置还包括连接到第一子像素电极的多个第一开关装置，连接到开关装置的多个栅极线，连接到第一装置并在像素电极之间通过以传输数据电压的多条数据线 以及设置在像素电极与设置在像素电极两侧的数据线之间且与第一子像素电极重叠的第一和第二存储电极。

公开(公告)号：US20090190081A1

公开(公告)日：2009-07-30

申请号：US12362365

申请日：2009-01-29

Applicant: Jae-Hyun Kim ,  Gee-Bum Kim ,  Ae Shin

Inventor： Jae-Hyun Kim ,  Gee-Bum Kim ,  Ae Shin

IPC: G02F1/1343

CPC classification number: G02F1/133707 ,  G02F1/136213

Abstract: A liquid crystal display includes a first insulating substrate, a gate line and a data line provided on the first insulating substrate to cross each other, a first sub-pixel electrode coupled to the gate line and the data line, a second sub-pixel electrode capacitively connected to the first sub-pixel electrode, a second insulating substrate opposite to and facing the first insulating substrate, a common electrode formed on the second insulating substrate, and a cut-out pattern formed on the common electrode.

Abstract translation: 液晶显示器包括第一绝缘基板，栅极线和设置在第一绝缘基板上以彼此交叉的数据线，耦合到栅极线和数据线的第一子像素电极，第二子像素电极 电容连接到第一子像素电极，与第一绝缘基板相对并面对第二绝缘基板，形成在第二绝缘基板上的公共电极和形成在公共电极上的切口图案。

公开(公告)号：US20070194317A1

公开(公告)日：2007-08-23

申请号：US11619405

申请日：2007-01-03

Applicant: Ji-Suk Lim ,  Ae Shin

Inventor： Ji-Suk Lim ,  Ae Shin

IPC: H01L29/04

CPC classification number: G02F1/136204 ,  H01L27/0251 ,  H01L27/12 ,  H01L27/13

Abstract: An array substrate includes a base substrate, a dummy circuit section, a dummy pixel portion, an extended line, a common voltage line, and an overlap portion. Pixel portions are formed in a display area. The dummy circuit section is formed in a peripheral area to protect the pixel portions from static electricity. The dummy pixel portion is adjacent to the dummy circuit section. The dummy circuit section is in an electrically floating state. The extended line is extended from the dummy circuit section and electrically open with respect to the dummy pixel portion. The common voltage line is overlapped with the extended line of the dummy circuit section, the extended line being electrically open with respect to the display area, and thus the display area may be protected from the static electricity which flows into the dummy circuit section.

Abstract translation: 阵列基板包括基底基板，虚拟电路部分，虚拟像素部分，延伸线，公共电压线和重叠部分。 像素部分形成在显示区域中。 伪电路部分形成在周边区域中，以保护像素部分免受静电。 伪像素部分与伪电路部分相邻。 虚拟电路部分处于电浮动状态。 延长线从虚拟电路部分延伸并相对于虚拟像素部分电开放。 公共电压线与虚拟电路部分的延伸线重叠，延伸线相对于显示区域电开，因此可以防止显示区域流入虚拟电路部分的静电。

公开(公告)号：US20060256248A1

公开(公告)日：2006-11-16

申请号：US11409589

申请日：2006-04-24

Applicant: Seung-soo Baek ,  Dong-gyu Kim ,  Ae Shin

Inventor： Seung-soo Baek ,  Dong-gyu Kim ,  Ae Shin

IPC: G02F1/136

CPC classification number: G02F1/136286 ,  G02F1/1393 ,  G02F2001/13606

Abstract: A thin film transistor (TFT) array panel for maintaining uniform parasitic capacitance occurring in individual pixels is provided. The thin film transistor array panel includes a gate line having a gate electrode disposed on an insulating substrate and extending in a row direction, a semiconductor layer disposed above and insulated from the gate electrode, a data line having a source electrode that at least partially overlaps with the semiconductor layer, the data line extending in a column direction, crossing the gate line, and insulated from the gate line, a drain electrode facing the source electrode around the gate electrode, at least partially overlapping with the semiconductor layer, and crossing over the gate electrode, and a pixel electrode disposed above and insulated from the resulting structure, the pixel electrode electrically connected to the drain electrode and divided into a plurality of small domains by a domain divider.

Abstract translation: 提供了用于保持在各个像素中发生的均匀寄生电容的薄膜晶体管（TFT）阵列面板。 薄膜晶体管阵列面板包括栅极线，栅极线设置在绝缘基板上并沿行方向延伸，半导体层设置在栅电极之上并与栅电极绝缘，数据线具有至少部分重叠的源电极 与半导体层一起，数据线在列方向上延伸，与栅极线交叉并与栅极线绝缘，与栅极电极相对的与源电极相对的漏电极，与半导体层至少部分重叠，并与之交叉 栅电极和设置在所得结构之上并与所述结构绝缘的像素电极，所述像素电极通过畴分隔器电连接到漏电极并分成多个小畴。