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公开(公告)号：US20070188664A1
公开(公告)日：2007-08-16
申请号：US11276130
申请日：2006-02-15
申请人： Ahmed Ginawi , Casey Grant , Christopher Ro , Sebastian Ventrone
发明人： Ahmed Ginawi , Casey Grant , Christopher Ro , Sebastian Ventrone
CPC分类号： H04N5/50 , H04N7/163 , H04N21/4383 , H04N21/4394 , H04N21/44008 , H04N21/472 , H04N21/812
摘要： Systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the system includes a microcontroller; a chooser for choosing a primary signal from a plurality of program-variable signals at the microcontroller; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition. A user can switch between signals such as television channels or other dedicated functions without the risk of missing a portion of the program material.
摘要翻译： 公开了用于在多个信号之间切换用于显示的显示信号的系统。 在一个实施例中，该系统包括微控制器; 用于在微控制器处从多个可编程信号中选择主信号的选择器; 耦合到微控制器的监视器调谐器，用于在将所显示的信号从主信号切换到辅助信号期间调谐主信号; 耦合到所述监视器调谐器和所述微控制器的检测器，用于检测所述主信号中的预定条件; 以及耦合到微控制器的选择器，用于在发生预定条件时将显示的信号从次级信号切换到主信号。 用户可以在诸如电视频道或其他专用功能的信号之间切换，而不会丢失节目素材的一部分。
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2.发明申请AN IMPROVED RECEIVER HAVING FULL SIGNAL PATH DIFFERENTIAL OFFSET CANCELLATION CAPABILITIES 失效具有完整信号路径的改进接收器差分偏移消除能力公开(公告)号：US20050212564A1
公开(公告)日：2005-09-29
申请号：US10906988
申请日：2005-03-15
CPC分类号： H03F3/45775 , G11C27/026
摘要： There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.
摘要翻译： 描述了一种改进的接收机，其首先包括模拟输入放大器，采样保持差分电路和串联连接的两级差分比较器，其中第一级由两个比较器和一个比较器的第二级组成。 通过用专用控制逻辑产生的信号正确激活开关，输入差分信号在取样和保持电路中被采样，以产生第一和第二差分信号。 第一差分信号保持第一状态，第二差分信号传播第二状态。 结果，由第二比较器级输出的信号反映差分偏移减去偏移补偿。
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3.发明授权公开(公告)号：US07872692B2
公开(公告)日：2011-01-18
申请号：US12056795
申请日：2008-03-27
CPC分类号： H04N7/163 , H04N21/4383 , H04N21/4394 , H04N21/44008 , H04N21/472 , H04N21/812
摘要： A design structure for systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes: a system for switching a displayed signal for a display between a plurality of signals, the system including: a microcontroller; a chooser for setting a primary signal from a plurality of program-variable signals; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition.
摘要翻译： 公开了用于在多个信号之间切换用于显示的显示信号的系统的设计结构。 在一个实施例中，设计结构体现在用于设计，制造或测试集成电路的机器可读介质中，并且包括：用于在多个信号之间切换用于显示的显示信号的系统，所述系统包括：微控制器 ; 用于从多个可编程信号设置主信号的选择器; 耦合到微控制器的监视器调谐器，用于在将所显示的信号从主信号切换到辅助信号期间调谐主信号; 耦合到所述监视器调谐器和所述微控制器的检测器，用于检测所述主信号中的预定条件; 以及耦合到微控制器的选择器，用于在发生预定条件时将显示的信号从次级信号切换到主信号。
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公开(公告)号：US07403054B1
公开(公告)日：2008-07-22
申请号：US11951217
申请日：2007-12-05
IPC分类号： H03K7/06
CPC分类号： H03L7/085 , H03K5/133 , H03K2005/00026 , H03L7/0812
摘要： A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, which results in clock edges in each cycle that are not located at the same phase locations in each of the M cycles. Any of the phase locations from any of the cycles can be used to generate a clock edge for all cycle in the system application. This requires a special technique to “lock” the DLL loop over a M cycle period instead of a one cycle period. The benefit is that it improves the clock placement granularity by a factor of M over the previous art.
摘要翻译： 一种在亚皮秒粒度下在延迟锁定环（DLL）中生成多相时钟的电路装置和方法。 本发明的电路和方法涉及将N个阶段DLL中的多个周期M锁定，例如M个周期，其中M是素数，其导致每个周期中不位于相同相位位置的时钟边沿 每个M个循环。 来自任何周期的任何相位位置都可用于为系统应用中的所有周期生成时钟边沿。 这需要一个特殊的技术来在一个M周期而不是一个周期周期内“锁定”DLL循环。 其优点在于，它比之前的技术将时钟布局粒度提高了M倍。
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公开(公告)号：US07773159B2
公开(公告)日：2010-08-10
申请号：US11276130
申请日：2006-02-15
CPC分类号： H04N5/50 , H04N7/163 , H04N21/4383 , H04N21/4394 , H04N21/44008 , H04N21/472 , H04N21/812
摘要： Systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the system includes a microcontroller; a chooser for choosing a primary signal from a plurality of program-variable signals at the microcontroller; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition. A user can switch between signals such as television channels or other dedicated functions without the risk of missing a portion of the program material.
摘要翻译： 公开了用于在多个信号之间切换用于显示的显示信号的系统。 在一个实施例中，该系统包括微控制器; 用于在微控制器处从多个可编程信号中选择主信号的选择器; 耦合到微控制器的监视器调谐器，用于在将所显示的信号从主信号切换到辅助信号期间调谐主信号; 耦合到所述监视器调谐器和所述微控制器的检测器，用于检测所述主信号中的预定条件; 以及耦合到微控制器的选择器，用于在发生预定条件时将显示的信号从次级信号切换到主信号。 用户可以在诸如电视频道或其他专用功能的信号之间切换，而不会丢失节目素材的一部分。
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6.发明申请DESIGN STRUCTURE FOR SWITCHING SYSTEM FOR SIGNAL MONITORING AND SWITCH-BACK CONTROL 有权用于信号监控和开关控制的开关系统的设计结构公开(公告)号：US20080172641A1
公开(公告)日：2008-07-17
申请号：US12056795
申请日：2008-03-27
IPC分类号： G06F17/50
CPC分类号： H04N7/163 , H04N21/4383 , H04N21/4394 , H04N21/44008 , H04N21/472 , H04N21/812
摘要： A design structure for systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes: a system for switching a displayed signal for a display between a plurality of signals, the system including: a microcontroller; a chooser for setting a primary signal from a plurality of program-variable signals; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition.
摘要翻译： 公开了用于在多个信号之间切换用于显示的显示信号的系统的设计结构。 在一个实施例中，设计结构体现在用于设计，制造或测试集成电路的机器可读介质中，并且包括：用于在多个信号之间切换用于显示的显示信号的系统，所述系统包括：微控制器 ; 用于从多个可编程信号设置主信号的选择器; 耦合到微控制器的监视器调谐器，用于在将所显示的信号从主信号切换到辅助信号期间调谐主信号; 耦合到所述监视器调谐器和所述微控制器的检测器，用于检测所述主信号中的预定条件; 以及耦合到微控制器的选择器，用于在发生预定条件时将显示的信号从次级信号切换到主信号。
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7.发明授权Receiver having full signal path differential offset cancellation capabilities 失效接收机具有全信号路径差分偏移消除功能公开(公告)号：US07180354B2
公开(公告)日：2007-02-20
申请号：US10906988
申请日：2005-03-15
IPC分类号： H03L5/00
CPC分类号： H03F3/45775 , G11C27/026
摘要： There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.
摘要翻译： 描述了一种改进的接收机，其首先包括模拟输入放大器，采样保持差分电路和串联连接的两级差分比较器，其中第一级由两个比较器和一个比较器的第二级组成。 通过用专用控制逻辑产生的信号正确激活开关，输入差分信号在取样和保持电路中被采样，以产生第一和第二差分信号。 第一差分信号保持第一状态，第二差分信号传播第二状态。 结果，由第二比较器级输出的信号反映差分偏移减去偏移补偿。
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公开(公告)号：US5923097A
公开(公告)日：1999-07-13
申请号：US900074
申请日：1997-07-24
CPC分类号： G01R31/2884 , Y10T307/391
摘要： An integrated circuit such as an application specific integrated circuit (ASIC) which has operational power supplies provided for different respective analog cores and digital logic and/or macros may be tested using on-chip power supplies, preferably comprising operational amplifiers connected as voltage followers and controlled by a band-gap voltage source or a voltage divider, drawing power from a single power supply to the chip which is generally provided in a standardized pin-out location. Disablement of respective operational amplifiers also provides electrical isolation of the respective cores during testing. A reduced pin-count is involved in the testing procedure since operational power supply connections can be open circuited or "tri-stated". On-chip power supplies for testing provides power while avoiding a need to provide low-noise power supplies and/or complex switching in a test system or to utilize custom front-end boards or both to provide power to arbitrary chip or package connections.
摘要翻译： 可以使用片上电源（其优选地包括作为电压跟随器连接的运算放大器）来测试诸如专用集成电路（ASIC）的集成电路，其具有为不同的相应的模拟核心和数字逻辑和/或宏提供的操作电源， 由带隙电压源或分压器控制，从单个电源向芯片提供功率，该芯片通常设置在标准的引脚输出位置。 各种运算放大器的禁用在测试期间还提供各个核的电隔离。 由于操作电源连接可以开路或“三态”，所以测试过程涉及到减少的引脚数。 用于测试的片上电源提供电源，同时避免在测试系统中提供低噪声电源和/或复杂开关，或利用定制的前端板或两者来为任意的芯片或封装连接提供电源。
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