公开(公告)号：US07403054B1

公开(公告)日：2008-07-22

申请号：US11951217

申请日：2007-12-05

申请人： Anjali R. Malladi ,  Christopher Ro ,  Stephen D. Wyatt

发明人： Anjali R. Malladi ,  Christopher Ro ,  Stephen D. Wyatt

IPC分类号： H03K7/06

CPC分类号： H03L7/085 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0812

摘要： A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, which results in clock edges in each cycle that are not located at the same phase locations in each of the M cycles. Any of the phase locations from any of the cycles can be used to generate a clock edge for all cycle in the system application. This requires a special technique to “lock” the DLL loop over a M cycle period instead of a one cycle period. The benefit is that it improves the clock placement granularity by a factor of M over the previous art.

摘要翻译： 一种在亚皮秒粒度下在延迟锁定环（DLL）中生成多相时钟的电路装置和方法。 本发明的电路和方法涉及将N个阶段DLL中的多个周期M锁定，例如M个周期，其中M是素数，其导致每个周期中不位于相同相位位置的时钟边沿 每个M个循环。 来自任何周期的任何相位位置都可用于为系统应用中的所有周期生成时钟边沿。 这需要一个特殊的技术来在一个M周期而不是一个周期周期内“锁定”DLL循环。 其优点在于，它比之前的技术将时钟布局粒度提高了M倍。

公开(公告)号：US5923097A

公开(公告)日：1999-07-13

申请号：US900074

申请日：1997-07-24

申请人： Michael P. Corriveau ,  Christopher Ro ,  Stephen D. Wyatt

发明人： Michael P. Corriveau ,  Christopher Ro ,  Stephen D. Wyatt

IPC分类号： G01R31/28 ,  G01R31/00

CPC分类号： G01R31/2884 ,  Y10T307/391

摘要： An integrated circuit such as an application specific integrated circuit (ASIC) which has operational power supplies provided for different respective analog cores and digital logic and/or macros may be tested using on-chip power supplies, preferably comprising operational amplifiers connected as voltage followers and controlled by a band-gap voltage source or a voltage divider, drawing power from a single power supply to the chip which is generally provided in a standardized pin-out location. Disablement of respective operational amplifiers also provides electrical isolation of the respective cores during testing. A reduced pin-count is involved in the testing procedure since operational power supply connections can be open circuited or "tri-stated". On-chip power supplies for testing provides power while avoiding a need to provide low-noise power supplies and/or complex switching in a test system or to utilize custom front-end boards or both to provide power to arbitrary chip or package connections.

摘要翻译： 可以使用片上电源（其优选地包括作为电压跟随器连接的运算放大器）来测试诸如专用集成电路（ASIC）的集成电路，其具有为不同的相应的模拟核心和数字逻辑和/或宏提供的操作电源， 由带隙电压源或分压器控制，从单个电源向芯片提供功率，该芯片通常设置在标准的引脚输出位置。 各种运算放大器的禁用在测试期间还提供各个核的电隔离。 由于操作电源连接可以开路或“三态”，所以测试过程涉及到减少的引脚数。 用于测试的片上电源提供电源，同时避免在测试系统中提供低噪声电源和/或复杂开关，或利用定制的前端板或两者来为任意的芯片或封装连接提供电源。

公开(公告)号：US07583116B2

公开(公告)日：2009-09-01

申请号：US11833500

申请日：2007-08-03

申请人： Stephen D. Wyatt ,  Tian Xia

发明人： Stephen D. Wyatt ,  Tian Xia

IPC分类号： H03L7/06

CPC分类号： H03L7/0896 ,  H02M3/07 ,  H03L7/18

摘要： Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.

摘要翻译： 公开了当前的电流源和源极电路，它们组合的电荷泵以及结合电荷泵的锁相环。 电流源和电源电路各自具有偏置连接到输出节点的晶体管的电流镜。 这些电路还具有两级反馈放大器以感测电流镜漏极电压并控制晶体管栅极电压，以便稳定电流镜漏极电压，而与输出节点处的输出电压无关。 放大器还增加输出节点的输出电阻。 该配置允许宽的工作电压范围，并在非常低的电源下确保良好的电路性能。 集成这些电路的电荷泵产生高度匹配的充电和放电电流。 集成该电荷泵的PLL具有最小的带宽偏移和最小的锁定速度和抖动性能下降。

公开(公告)号：US20090033407A1

公开(公告)日：2009-02-05

申请号：US11845249

申请日：2007-08-27

申请人： Stephen D. Wyatt ,  Tian Xia

发明人： Stephen D. Wyatt ,  Tian Xia

IPC分类号： G05F1/10

CPC分类号： H03L7/0896 ,  H02M3/07 ,  H03L7/18

摘要： Disclosed are design structures for current sink and source circuits, a charge pump, and a phase locked loop. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.

摘要翻译： 公开了电流吸收和电源电路，电荷泵和锁相环的设计结构。 电流源和电源电路各自具有偏置连接到输出节点的晶体管的电流镜。 这些电路还具有两级反馈放大器以感测电流镜漏极电压并控制晶体管栅极电压，以便稳定电流镜漏极电压，而与输出节点处的输出电压无关。 放大器还增加输出节点的输出电阻。 该配置允许宽的工作电压范围，并在非常低的电源下确保良好的电路性能。 集成这些电路的电荷泵产生高度匹配的充电和放电电流。 集成该电荷泵的PLL具有最小的带宽偏移和最小的锁定速度和抖动性能下降。

公开(公告)号：US20080012549A1

公开(公告)日：2008-01-17

申请号：US11424881

申请日：2006-06-19

申请人： Brandon R. Kam ,  Stephen D. Wyatt

发明人： Brandon R. Kam ,  Stephen D. Wyatt

IPC分类号： G01R23/175 ,  H03L7/06

CPC分类号： G01R31/31709 ,  G01R29/26 ,  H03L7/07 ,  H03L7/0814

摘要： Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

摘要翻译： 本文公开了改进的内置自测试（BIST）电路和用于测量时钟信号的相位和/或周期到周期抖动的相关方法的实施例。 BIST电路的实施例实现了可变游标数字延迟锁定线方法。 具体地，BIST电路的实施例包括数字延迟锁定环和游标延迟线，分别用于电路的粗调和微调部分。 此外，BIST电路是可变的，因为电路的分辨率由芯片变为芯片，而数字是由标准数字逻辑元件实现的。

公开(公告)号：US08126041B2

公开(公告)日：2012-02-28

申请号：US11874960

申请日：2007-10-19

申请人： Brandon R. Kam ,  Stephen D. Wyatt

发明人： Brandon R. Kam ,  Stephen D. Wyatt

IPC分类号： H04B17/00

CPC分类号： G01R31/31709 ,  G01R29/26 ,  H03L7/07 ,  H03L7/0814

摘要： Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

摘要翻译： 本文公开了改进的内置自测试（BIST）电路和用于测量时钟信号的相位和/或周期到周期抖动的相关方法的实施例。 BIST电路的实施例实现了可变游标数字延迟锁定线方法。 具体地，BIST电路的实施例包括数字延迟锁定环和游标延迟线，分别用于电路的粗调和微调部分。 此外，BIST电路是可变的，因为电路的分辨率由芯片变为芯片，而数字是由标准数字逻辑元件实现的。

公开(公告)号：US07932774B2

公开(公告)日：2011-04-26

申请号：US12053958

申请日：2008-03-24

申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

IPC分类号： H03K5/00

CPC分类号： G05F1/56

摘要： A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.

摘要翻译： 用于模拟电源噪声滤波的固有RC功率分配的设计结构。 该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括电压调节器; 耦合到电压调节器的可变电阻器; 以及向可变电阻器提供反馈回路的性能监视和控制电路。

公开(公告)号：US07701270B2

公开(公告)日：2010-04-20

申请号：US11845249

申请日：2007-08-27

申请人： Stephen D. Wyatt ,  Tian Xia

发明人： Stephen D. Wyatt ,  Tian Xia

IPC分类号： H03L7/06

CPC分类号： H03L7/0896 ,  H02M3/07 ,  H03L7/18

摘要： Disclosed are design structures for current sink and source circuits, a charge pump, and a phase locked loop. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.

摘要翻译： 公开了电流吸收和电源电路，电荷泵和锁相环的设计结构。 电流源和电源电路各自具有偏置连接到输出节点的晶体管的电流镜。 这些电路还具有两级反馈放大器以感测电流镜漏极电压并控制晶体管栅极电压，以便稳定电流镜漏极电压，而与输出节点处的输出电压无关。 放大器还增加输出节点的输出电阻。 该配置允许宽的工作电压范围，并在非常低的电源下确保良好的电路性能。 集成这些电路的电荷泵产生高度匹配的充电和放电电流。 集成该电荷泵的PLL具有最小的带宽偏移和最小的锁定速度和抖动性能下降。

公开(公告)号：US20090243733A1

公开(公告)日：2009-10-01

申请号：US12057686

申请日：2008-03-28

申请人： Wagdi W. Abadeer ,  John A. Fifield ,  Stephen D. Wyatt

发明人： Wagdi W. Abadeer ,  John A. Fifield ,  Stephen D. Wyatt

IPC分类号： H03L7/00

CPC分类号： H03L7/099

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.

摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括用于确定输入电压对输出频率响应的非线性特性的第一结构，第一设计结构提供与输入电压的基于隧道的电流关系。 还公开了一种实现这种结构的系统和方法。

公开(公告)号：US20080244479A1

公开(公告)日：2008-10-02

申请号：US12053958

申请日：2008-03-24

申请人： Anthony R. BONACCIO ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

发明人： Anthony R. BONACCIO ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

IPC分类号： G06F17/50

CPC分类号： G05F1/56

摘要： A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.

摘要翻译： 用于模拟电源噪声滤波的固有RC功率分配的设计结构。 该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 设计结构包括电压调节器; 耦合到电压调节器的可变电阻器; 以及向可变电阻器提供反馈回路的性能监视和控制电路。