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    Method and system for resequencing data packets switched through a parallel packet switch
    1.
    发明授权
    Method and system for resequencing data packets switched through a parallel packet switch 有权
    通过并行分组交换机切换数据分组重新排序的方法和系统

    公开(公告)号：US07403536B2

    公开(公告)日：2008-07-22

    申请号：US10722901

    申请日：2003-11-26

    申请人： Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Daniel Wind

    发明人： Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Daniel Wind

    IPC分类号： H04L12/56

    CPC分类号： H04L49/153 ,  H04L12/5601 ,  H04L49/1523 ,  H04L49/30 ,  H04L49/3045 ,  H04L49/3081 ,  H04L49/50 ,  H04L2012/565 ,  H04L2012/5679 ,  H04L2012/568

    摘要： A method to resequence packets includes sequentially allocating in each source ingress adapter a packet rank to each packet received within each source ingress adapter. In each destination egress adapter, each ranked data packet is stored at a respective buffer address of an egress buffer. The respective buffer addresses of data packets received by a same source ingress adapter with a same priority level and switched through a same switching plane are linked in a same linked-list. The respective buffer addresses are preferably linked by their order of use in the egress buffer, and thus each linked-list is having a head list pointing to the oldest buffer address. The linked-lists are sorted into subsets including those linked-lists linking the respective buffer addresses of data packets received by a same source ingress adapter with a same priority level. For each subset of linked-lists, the packet ranks of the data packets stored at the buffer address pointed by the head lists of each linked-list of each subset are compared to determine the next data packet to be put in a sequence.

    摘要翻译： 重新分配分组的方法包括在每个源入口适配器中顺序分配每个源入口适配器中接收的每个分组的分组等级。 在每个目的地出口适配器中，每个排序的数据分组被存储在出口缓冲器的相应缓冲器地址处。 具有相同优先级的相同源入口适配器接收的并通过相同交换平面切换的数据分组的相应缓冲器地址被链接在相同的链表中。 相应的缓冲器地址优选地通过它们在出口缓冲器中的使用顺序来链接，因此每个链表都具有指向最旧缓冲器地址的头列表。 链接列表被分类为包括链接列表的链接列表，其链接相同的源入口适配器接收的数据分组的相应缓冲器地址具有相同的优先级。 对于链接列表的每个子集，比较存储在由每个子集的每个链表的头列表指向的缓冲地址处的数据分组的分组等级以确定要放入序列的下一个数据分组。

    Queue scheduling mechanism in a data packet transmission system
    2.
    发明授权
    Queue scheduling mechanism in a data packet transmission system 失效
    数据包传输系统中的队列调度机制

    公开(公告)号：US07382792B2

    公开(公告)日：2008-06-03

    申请号：US10065808

    申请日：2002-11-21

    申请人： Alain Blanc ,  Bernard Brezzo ,  Rene Gallezot ,  Francois Le Mauf ,  Daniel Wind

    发明人： Alain Blanc ,  Bernard Brezzo ,  Rene Gallezot ,  Francois Le Mauf ,  Daniel Wind

    IPC分类号： H04L12/28

    CPC分类号： H04L47/6215 ,  H04L47/2458 ,  H04L47/28 ,  H04L47/50 ,  H04L47/527 ,  H04L47/6285 ,  H04W28/14 ,  H04W72/1242

    摘要： A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank, and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides at each packet cycle a value N defining the priority rank to be considered by the queue scheduler whereby a data packet is read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.

    摘要翻译： 在数据分组传输系统中的队列调度机制，包括用于发送数据分组的传输设备的数据分组传输系统，用于接收数据分组的接收设备，分别与一组优先级相关联的一组队列设备，每个优先级由 用于将由传输设备发送的每个数据分组存储到与其优先级相对应的队列设备中的优先等级，以及队列调度器，用于在每个分组周期读取由普通优先级抢占算法确定的队列中的一个队列中的分组。 队列调度机制包括在每个分组周期提供定义要由队列调度器考虑的优先级的值N的信用设备，由队列调度器从对应于优先级N的队列设备读取数据分组，而不是 队列设备由普通优先级抢占算法确定。

    Queue scheduling mechanism in a data packet transmission system
    3.
    发明授权
    Queue scheduling mechanism in a data packet transmission system 失效
    数据包传输系统中的队列调度机制

    公开(公告)号：US07385993B2

    公开(公告)日：2008-06-10

    申请号：US10065809

    申请日：2002-11-21

    申请人： Alain Blanc ,  Rene Gallezot ,  Francois Le Maut ,  Daniel Wind

    发明人： Alain Blanc ,  Rene Gallezot ,  Francois Le Maut ,  Daniel Wind

    IPC分类号： H04L12/56

    CPC分类号： H04L47/6215 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/245 ,  H04L47/39 ,  H04L47/50 ,  H04L47/626

    摘要： A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides, at each packet cycle, a value N defining the priority rank to be read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm. The queue scheduling mechanism further includes an exhaustive priority register that registers the value of at least one exhaustive priority rank to be read by the queue scheduler from the queue device corresponding to the exhaustive priority rank rather than from the queue device corresponding to the priority N.

    摘要翻译： 在数据分组传输系统中的队列调度机制，包括用于发送数据分组的传输设备的数据分组传输系统，用于接收数据分组的接收设备，分别与一组优先级相关联的一组队列设备，每个优先级由 用于将由传输设备发送的每个数据分组存储到与其优先级相对应的队列设备中的优先等级，以及队列调度器，用于在每个分组周期读取由普通优先级抢占算法确定的队列中的一个队列中的分组。 队列调度机制包括在每个分组周期提供定义队列调度器从对应于优先级N的队列设备中读取的优先等级的值N，而不是由正常优先级抢占确定的队列设备的信用设备 算法。 队列调度机制还包括一个穷举优先级寄存器，其向与队列调度器读取的至少一个穷举优先等级的值进行比较，该队列设备对应于穷举优先级而不是来自对应于优先级N的队列设备。

    Multi-module switching system
    6.
    发明授权
    Multi-module switching system 有权
    多模块交换系统

    公开(公告)号：US07187685B2

    公开(公告)日：2007-03-06

    申请号：US10215812

    申请日：2002-08-08

    申请人： Daniel Wind

    发明人： Daniel Wind

    IPC分类号： G06F15/16 ,  H04J3/06

    CPC分类号： H04L49/15 ,  H04L49/103 ,  H04L49/25 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/45

    摘要： A multi-module switching system comprising at least two switching modules adapted for receiving data packets from at least one input adapter and transmitting the data packets to at least one output adapter, each of the switching modules including a shared buffer for buffering a portion of a data packet received from an input adapter and transmitting the portion to an output adapter. One of the switching modules is a master module receiving a portion of a data packet containing a packet header and sending control information contained therein serially to each other switching module as a slave module. Each slave module includes a delay computing structure adapted for computing a delay needed to transmit the control information from the master module to this slave module and a first storing structure adapted for storing a portion of a data packet transmitted from an input adapter to the slave module during the delay, before transmitting the portion to a respective shared buffer such that the portion of data packet is not received by the shared buffer before the slave module has received the control information from the master module.

    摘要翻译： 一种多模块交换系统，包括至少两个交换模块，适于从至少一个输入适配器接收数据分组，并将数据分组发送到至少一个输出适配器，每个交换模块包括一个共享缓冲器，用于缓冲一部分 从输入适配器接收的数据分组并将该部分发送到输出适配器。 其中一个交换模块是主模块，其接收包含分组报头的数据分组的一部分，并将包含在其中的控制信息串行地发送给彼此的切换模块作为从模块。 每个从模块包括适于计算从主模块向该从模块发送控制信息所需的延迟的延迟计算结构，以及适于将从输入适配器发送的数据分组的一部分存储到从模块的第一存储结构 在所述延迟期间，在将所述部分发送到相应的共享缓冲器之前，使得所述部分数据分组在所述从模块已经从所述主模块接收到所述控制信息之前未被所述共享缓冲器接收。

    Method and system for flexible network processor scheduler and data flow
    7.
    发明申请
    Method and system for flexible network processor scheduler and data flow 失效
    灵活的网络处理器调度器和数据流的方法和系统

    公开(公告)号：US20070011223A1

    公开(公告)日：2007-01-11

    申请号：US11133477

    申请日：2005-05-18

    申请人： Jean Calvignac ,  Chih-jen Chang ,  Joseph Logan ,  Fabrice Verplanken ,  Daniel Wind

    发明人： Jean Calvignac ,  Chih-jen Chang ,  Joseph Logan ,  Fabrice Verplanken ,  Daniel Wind

    IPC分类号： G06F15/16

    CPC分类号： H04L47/527 ,  H04L47/50 ,  H04L47/522 ,  H04L47/568 ,  H04L47/58

    摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

    摘要翻译： 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

    Scanner interface for the line adapters of a communication controller
    8.
    发明授权
    Scanner interface for the line adapters of a communication controller 失效
    扫描仪界面，用于通信控制器的线路适配器

    公开(公告)号：US5010548A

    公开(公告)日：1991-04-23

    申请号：US297730

    申请日：1989-01-17

    申请人： Yves Granger ,  Daniel Wind

    发明人： Yves Granger ,  Daniel Wind

    IPC分类号： G06F13/22 ,  G06F13/38

    CPC分类号： G06F13/225 ,  G06F13/385

    摘要： A line-adapter of a communications controller includes, for scanning the teleprocessing lines connected to it, cyclic scanning means FES exchanging information with the lines through a serial bidirectional link on which data and control informations are partitioned into frames and slots. Since both the FES and the serial link work with their own timings, an interface FESA is provided to adapt the FES scanning to the serial link structure. This FESA includes temporary storage means for storing on the one hand, data and control information transmitted from the LICs to the FES (10) through the inbound serial link, and on the other hand, data and control information transmitted from the FES to the LICs through the outbound serial link. The access of the FES, the outbound and inbound serial link to the storage means is time-shared and granted by an arbitration logic, according to the relative priorities of operation of said elements within the line-adapter of the communications controller.